ps2_mouse.tan.summary

基于fpga和sopc的用VHDL语言编写的EDA的PS/2鼠标键盘控制模块

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.939 ns
From           : reset
To             : lpm_counter:\GenSpkS:Count11[0]_rtl_2|cntr_7t7:auto_generated|safe_q[4]
From Clock     : 
To Clock       : CLK1
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 22.384 ns
From           : altsyncram:reduce_or_rtl_4|altsyncram_s7k:auto_generated|ram_block1a3~porta_address_reg7
To             : CODE1[2]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 19.196 ns
From           : reset
To             : CODE1[3]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.081 ns
From           : ps2_data
To             : always_one
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.610 ns
From           : ps2_clk_s
To             : ps2_clk
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.637 ns
From           : reset
To             : ps2_data2A[6]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 126.90 MHz ( period = 7.880 ns )
From           : lpm_counter:count_rtl_0|cntr_qu7:auto_generated|safe_q[3]
To             : q_data2_x[8]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'CLK1'
Slack          : N/A
Required Time  : None
Actual Time    : 176.06 MHz ( period = 5.680 ns )
From           : lpm_counter:\GenSpkS:Count11[0]_rtl_2|cntr_7t7:auto_generated|safe_q[4]
To             : lpm_counter:\GenSpkS:Count11[0]_rtl_2|cntr_7t7:auto_generated|safe_q[0]
From Clock     : CLK1
To Clock       : CLK1
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : m2_state~21
To             : m2_nexts~39
From Clock     : clk
To Clock       : clk
Failed Paths   : 742

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 742

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