dds.map.summary

来自「基于fpga和sopc的用VHDL语言编写的EDA的DDS信号发生器」· SUMMARY 代码 · 共 12 行

Flow Status : Successful - Tue Aug 02 11:36:22 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : dds
Top-level Entity Name : DDS
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Production
Total logic elements : 562
Total pins : 24
Total memory bits : 28,672
Total PLLs : 0