dds.tan.summary

基于fpga和sopc的用VHDL语言编写的EDA的DDS信号发生器

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.641 ns
From           : FWORD[0]
To             : REG32B:u2|DOUT[31]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.624 ns
From           : SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_qqs:auto_generated|altsyncram_kna2:altsyncram1|ram_block3a9~porta_address_reg9
To             : FOUT[9]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 5.232 ns
From           : CLK
To             : DA_CLK
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.639 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10]
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.603 ns
From           : SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_qqs:auto_generated|altsyncram_kna2:altsyncram1|ram_block3a7~porta_address_reg9
To             : FOUT[7]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 107.81 MHz ( period = 9.276 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3]
To             : sld_hub:sld_hub_inst|HUB_TDO~reg0
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 148.72 MHz ( period = 6.724 ns )
From           : SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_qqs:auto_generated|altsyncram_kna2:altsyncram1|ram_block3a9~porta_address_reg9
To             : sld_signaltap:dds1|acq_trigger_in_reg[9]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------