freqtest.tlg

来自「基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯」· TLG 代码 · 共 17 行

Synthesizing work.freqtest.struc
@W:"d:\k30demo\sendfre\freqtest.vhd":23:10:23:14|Unbound component mapped to black box
@W:"d:\k30demo\sendfre\freqtest.vhd":69:2:69:4|Port carry_out of entity work.cnt10 is unconnected
@W:"d:\k30demo\sendfre\freqtest.vhd":72:8:72:14|Incomplete sensitivity list - assuming completeness
@W:"d:\k30demo\sendfre\freqtest.vhd":75:36:75:39|Referenced variable dout is not in sensitivity list
Synthesizing work.cnt10.black_box
Post processing for work.cnt10.black_box
Synthesizing work.reg32b.behav
Post processing for work.reg32b.behav
Synthesizing work.testctl.behav
Post processing for work.testctl.behav
Post processing for work.freqtest.struc
@W:"d:\k30demo\sendfre\freqtest.vhd":74:8:74:11|Latch generated from process for signal k3, probably caused by a missing assignment in an if or case stmt
@W:"d:\k30demo\sendfre\freqtest.vhd":74:8:74:11|Latch generated from process for signal k2, probably caused by a missing assignment in an if or case stmt
@W:"d:\k30demo\sendfre\freqtest.vhd":74:8:74:11|Latch generated from process for signal k1, probably caused by a missing assignment in an if or case stmt
@W:"d:\k30demo\sendfre\freqtest.vhd":74:8:74:11|Latch generated from process for signal dlow(3 downto 0), probably caused by a missing assignment in an if or case stmt