testctl.edf

来自「基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯」· EDF 代码 · 共 101 行

(edif TESTCTL
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2001 9 9 1 26 44)
      (author "Synplicity, Inc.")
      (program "Synplify" (version "5.1.2"))
     )
   )
  (library ALTERA
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell S_DFF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port CLK (direction INPUT))
           (port CLRN (direction INPUT))
           (port PRN (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell LUT (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port IN1 (direction INPUT))
           (port IN2 (direction INPUT))
           (port IN3 (direction INPUT))
           (port IN4 (direction INPUT))
           (port A_OUT (direction OUTPUT))
         )
       )
    )
  )
  (library (rename PRIMLIB "PrimLib")
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell INV1 (cellType GENERIC)
      (view PRIM (viewType NETLIST)
        (interface
         (port OUT0 (direction OUTPUT))
         (port I0 (direction INPUT))
        )
      )
    )
  )
  (library (rename WORK "work")
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell TESTCTL (cellType GENERIC)
       (view (rename BEHAV "behav") (viewType NETLIST)
         (interface
           (port CLK (direction INPUT))
           (port TSTEN (direction OUTPUT))
           (port CLR_CNT (direction OUTPUT))
           (port (rename LOAD "Load") (direction OUTPUT))
         )
         (contents
          (instance (rename TSTEN1 "TSTEN") (viewRef PRIM (cellref S_DFF (libraryRef ALTERA))))
          (instance (rename UN2_CLK "un2_clk") (viewRef PRIM (cellref LUT (libraryRef ALTERA)))
 (property lut_function (string "((IN2' IN1'))"))
)
          (instance (rename TSTEN_I_L "TSTEN_i_L") (viewRef PRIM (cellref INV1 (libraryRef PRIMLIB))))
          (net CLK (joined
           (portRef IN1 (instanceRef UN2_CLK))
           (portRef CLK)
           (portRef CLK (instanceRef TSTEN1))
          ))
          (net TSTEN (joined
           (portRef I0 (instanceRef TSTEN_I_L))
           (portRef IN2 (instanceRef UN2_CLK))
           (portRef Q (instanceRef TSTEN1))
           (portRef TSTEN)
          ))
          (net VCC (joined
           (portRef PRN (instanceRef TSTEN1))
           (portRef CLRN (instanceRef TSTEN1))
          ))
          (net GND (joined
           (portRef IN4 (instanceRef UN2_CLK))
           (portRef IN3 (instanceRef UN2_CLK))
          ))
          (net CLR_CNT (joined
           (portRef A_OUT (instanceRef UN2_CLK))
           (portRef CLR_CNT)
          ))
          (net (rename LOAD "Load") (joined
           (portRef OUT0 (instanceRef TSTEN_I_L))
           (portRef D (instanceRef TSTEN1))
           (portRef LOAD)
          ))
         )
       )
    )
  )
  (design TESTCTL (cellRef TESTCTL (libraryRef WORK)))
)