cnt10.vhd

来自「基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯」· VHDL 代码 · 共 35 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
    PORT (CLK : IN STD_LOGIC;                     -- 时钟信号
        CLR : IN STD_LOGIC;                       -- 清零信号
        ENA : IN STD_LOGIC;                       -- 计数使能信号
        CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);           -- 计数结果
        CARRY_OUT : OUT STD_LOGIC    );           -- 计数进位
   END CNT10;
ARCHITECTURE behav OF CNT10 IS
    SIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);  
BEGIN
    PROCESS(CLK, CLR, ENA)
      BEGIN
        IF CLR = '1' THEN   CQI <= "0000";             -- 清零
        ELSIF CLK'EVENT AND CLK = '1' THEN
            IF ENA = '1' THEN
                IF CQI < "1001" THEN   CQI <= CQI + 1;   
                  ELSE            CQI <= "0000";       -- 等于9，则回转
                END IF;
            END IF;
        END IF;
    END PROCESS;
    PROCESS(CQI)
    BEGIN
        IF CQI = "1001" THEN CARRY_OUT <= '1';
        ELSE
            CARRY_OUT <= '0';
        END IF;
    END PROCESS;
    CQ <= CQI;
END behav;