testctl.srr

基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯

$ Start of Compile
#Sun Sep 09 01:26:41 2001

Synplify VHDL Compiler, version 5.1.2, built Apr 14 1999
Copyright (C) 1994-1999, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!
Synthesizing work.testctl.behav
Post processing for work.testctl.behav
@END
Process took 0.44 seconds realtime, 0.44 seconds cputime
Synplify Altera Technology Mapper, version 5.1.2, built Apr 14 1999
Copyright (C) 1994-1998, Synplicity Inc.  All Rights Reserved
Loading timing data for chip EPF10K20-3
List of partitions to map:
   view:work.TESTCTL(behav)
Loading timing data for chip EPF10K20-3

		 ##### START TIMING REPORT #####
Set the Environment Variable SYNPLIFY_TIMING_REPORT_OLD to get the old timing report 


		 Performance Summary 
		*********************

           Requested     Estimated     Requested     Estimated          
Clock      Frequency     Frequency     Period        Period        Slack
------------------------------------------------------------------------
System     1.0 MHz       357.1 MHz     1000.0        2.8           997.2
CLK        1.0 MHz       107.5 MHz     1000.0        9.3           990.7
========================================================================


		 Interface Information 
		***********************

Input Ports: 

Port     Reference     User           Arrival     Required          
Name     Clock         Constraint     Time        Time         Slack
--------------------------------------------------------------------
====================================================================


Output Ports: 

Port        Reference     User           Arrival     Required          
Name        Clock         Constraint     Time        Time         Slack
-----------------------------------------------------------------------
CLR_CNT     CLK           0.0            6.7         1000.0       993.3
Load        CLK           0.0            7.1         1000.0       992.9
TSTEN       CLK           0.0            3.9         1000.0       996.1
=======================================================================


		Detailed Timing Report for  clock : System 
		*******************************************
Requested Period 	  1000.0 ns
Estimated Period 	  2.8 ns
Worst Slack 	 	 997.2 ns

Start Points for Paths with Slack Worse than 999.4 ns : 

                                      Arrival          
Instance     Type     Pin     Net     Time        Slack
-------------------------------------------------------
CLK          Port     CLK     CLK     0.0         997.2
=======================================================


No End Points with Slack Worse than 999.4 ns Found


A Critical Path with worst case slack = 997.2 ns:  

Instance/Net               Pin         Pin     Arrival     Delta     Fan
Name             Type      Name        Dir     Time        Delay     Out
------------------------------------------------------------------------
CLK              Port      CLK         Out                 0.0          
CLK              Net                                                 2  
un2_clk          S_LUT     I0          In      0.0                      
un2_clk          S_LUT     OUT         Out                 6.7          
un2_clk          Net                                                 1  
CLR_CNT          Port      CLR_CNT     In      6.7                      
========================================================================


		Detailed Timing Report for  clock : CLK 
		*******************************************
Requested Period 	  1000.0 ns
Estimated Period 	  9.3 ns
Worst Slack 	 	 990.7 ns

Start Points for Paths with Slack Worse than 992.9 ns : 

                                         Arrival          
Instance     Type      Pin     Net       Time        Slack
----------------------------------------------------------
TSTEN        S_DFF     Q       TSTEN     3.9         990.7
==========================================================


End Points for Paths with Slack Worse than 992.9 ns : 

                                            Required          
Instance     Type      Pin      Net         Time         Slack
--------------------------------------------------------------
Load         Port      Load     TSTEN_i     1000.0       992.9
TSTEN        S_DFF     D        TSTEN_i     997.8        990.7
==============================================================


A Critical Path with worst case slack = 990.7 ns:  

Instance/Net               Pin      Pin     Arrival     Delta     Fan
Name             Type      Name     Dir     Time        Delay     Out
---------------------------------------------------------------------
TSTEN            S_DFF     Q        Out                 3.9          
TSTEN            Net                                              3  
TSTEN_i          S_LUT     I0       In      3.9                      
TSTEN_i          S_LUT     OUT      Out                 3.2          
TSTEN_i          Net                                              2  
TSTEN            S_DFF     D        In      7.1                      
=====================================================================


		 ##### END TIMING REPORT #####


---------------------------------------
Resource Usage Report

Synplify is performing all technology mapping
Post place and route resource use may vary a small
amount due to logic cell replication and register packing
decisions during place and route.

Design view:work.TESTCTL(behav)
Selecting part epf10k20tc144-3

Logic resources:  2 LCs of 1152 ( 0%)
Number of Nets:   6
Number of Inputs: 8
Register bits:   1
I/O cells:       4

Details:
Cells in logic mode:   2
Cells in arith mode:   0
Cells in cascade mode: 0
Cells in counter mode: 0
LUTs driving both DFF and logic: 1


Creating updateacf script d:\k30demo\sendfre\testctl.sat to pass constraints to MAX+plusII
All Constraints processed!
Mapper successful!
Process took 1.98 seconds realtime, 1.98 seconds cputime