testctl.srs

来自「基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯」· SRS 代码 · 共 44 行

#
#
#
# Created by Synplify VHDL Compiler version 5.1.2 from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Sun Sep 09 01:26:41 2001
#
#
#OPTIONS:"|-ram|-sm|-fid2|-sharing|on|-encrypt|-ui|-lite|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"D:\\EDAPRO\\SYNPLCTY\\BIN\\C_VHDL.EXE":924105292l
#CUR:"D:\\EDAPRO\\SYNPLCTY\\lib\\vhd\\location.map":919797106l
#CUR:"D:\\EDAPRO\\SYNPLCTY\\lib\\vhd\\std.vhd":918155282l
#CUR:"d:\\k30demo\\sendfre\\freqtest.vhd":966378296l
#CUR:"D:\\EDAPRO\\SYNPLCTY\\lib\\vhd\\std1164.vhd":918155282l
#CUR:"d:\\k30demo\\sendfre\\cnt10.vhd":949416870l
#CUR:"d:\\k30demo\\sendfre\\reg32b.vhd":949412800l
#CUR:"d:\\k30demo\\sendfre\\testctl.vhd":949415054l
#CUR:"D:\\EDAPRO\\SYNPLCTY\\lib\\vhd\\unsigned.vhd":918155282l
#CUR:"D:\\EDAPRO\\SYNPLCTY\\lib\\vhd\\arith.vhd":918155282l
f "D:\EDAPRO\SYNPLCTY\lib\vhd\std.vhd"; # file 0
f "d:\k30demo\sendfre\freqtest.vhd"; # file 1
f "D:\EDAPRO\SYNPLCTY\lib\vhd\std1164.vhd"; # file 2
f "d:\k30demo\sendfre\cnt10.vhd"; # file 3
f "d:\k30demo\sendfre\reg32b.vhd"; # file 4
f "d:\k30demo\sendfre\testctl.vhd"; # file 5
f "D:\EDAPRO\SYNPLCTY\lib\vhd\unsigned.vhd"; # file 6
f "D:\EDAPRO\SYNPLCTY\lib\vhd\arith.vhd"; # file 7
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