freqtest.edf

来自「基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯」· EDF 代码 · 共 1,494 行 · 第 1/5 页

(edif FREQTEST
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2001 9 9 1 28 16)
      (author "Synplicity, Inc.")
      (program "Synplify" (version "5.1.2"))
     )
   )
  (library ALTERA
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell S_DFF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port CLK (direction INPUT))
           (port CLRN (direction INPUT))
           (port PRN (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell LUT (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port IN1 (direction INPUT))
           (port IN2 (direction INPUT))
           (port IN3 (direction INPUT))
           (port IN4 (direction INPUT))
           (port A_OUT (direction OUTPUT))
         )
       )
    )
    (cell LCELL (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port A_IN (direction INPUT))
           (port A_OUT (direction OUTPUT))
         )
       )
    )
    (cell CASCADE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port A_IN (direction INPUT))
           (port A_OUT (direction OUTPUT))
         )
       )
    )
  )
  (library LPM_LIBRARY
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell LATRS1 (cellType GENERIC)
       (view LPM (viewType NETLIST)
         (interface
           (port DATA0 (direction INPUT))
           (port GATE (direction INPUT))
           (port ASET (direction INPUT))
           (port ACLR (direction INPUT))
           (port Q0 (direction OUTPUT))
           (property LPM_WIDTH (integer 1))
           (property WIDTH (integer 1))
           (property LPM_TYPE (string "LPM_LATCH"))
         )
       )
    )
    (cell LAT1 (cellType GENERIC)
       (view LPM (viewType NETLIST)
         (interface
           (port DATA0 (direction INPUT))
           (port GATE (direction INPUT))
           (port Q0 (direction OUTPUT))
           (property LPM_WIDTH (integer 1))
           (property WIDTH (integer 1))
           (property LPM_TYPE (string "LPM_LATCH"))
         )
       )
    )
  )
  (library (rename PRIMLIB "PrimLib")
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell INV1 (cellType GENERIC)
      (view PRIM (viewType NETLIST)
        (interface
         (port OUT0 (direction OUTPUT))
         (port I0 (direction INPUT))
        )
      )
    )
    (cell AND2 (cellType GENERIC)
      (view PRIM (viewType NETLIST)
        (interface
         (port OUT (direction OUTPUT))
         (port I0 (direction INPUT))
         (port I1 (direction INPUT))
        )
      )
    )
  )
  (library (rename WORK "work")
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell (rename CNT10 "cnt10") (cellType GENERIC)
       (view (rename BLACK_BOX "black_box") (viewType NETLIST)
         (interface
           (port (array (rename CQ "CQ(3:0)") 4) (direction OUTPUT))
           (port CLK (direction INPUT))
           (port CLR (direction INPUT))
           (port ENA (direction INPUT))
           (port CARRY_OUT (direction OUTPUT))
         )
       )
    )
    (cell REG32B (cellType GENERIC)
       (view (rename NETLIST "netlist") (viewType NETLIST)
         (interface
           (port TSTEN1_I_0 (direction INPUT))
           (port DTO1_0 (direction INPUT))
           (port DTO1_1 (direction INPUT))
           (port DTO1_2 (direction INPUT))
           (port DTO1_3 (direction INPUT))
           (port DTO1_4 (direction INPUT))
           (port DTO1_5 (direction INPUT))
           (port DTO1_6 (direction INPUT))
           (port DTO1_7 (direction INPUT))
           (port DTO1_8 (direction INPUT))
           (port DTO1_9 (direction INPUT))
           (port DTO1_10 (direction INPUT))
           (port DTO1_11 (direction INPUT))
           (port DTO1_12 (direction INPUT))
           (port DTO1_13 (direction INPUT))
           (port DTO1_14 (direction INPUT))
           (port DTO1_15 (direction INPUT))
           (port DTO1_16 (direction INPUT))
           (port DTO1_17 (direction INPUT))
           (port DTO1_18 (direction INPUT))
           (port DTO1_19 (direction INPUT))
           (port DTO1_20 (direction INPUT))
           (port DTO1_21 (direction INPUT))
           (port DTO1_22 (direction INPUT))
           (port DTO1_23 (direction INPUT))
           (port DTO1_24 (direction INPUT))
           (port DTO1_25 (direction INPUT))
           (port DTO1_26 (direction INPUT))
           (port DTO1_27 (direction INPUT))
           (port DTO1_28 (direction INPUT))
           (port DTO1_29 (direction INPUT))
           (port DTO1_30 (direction INPUT))
           (port DTO1_31 (direction INPUT))
           (port DOUT0 (direction OUTPUT))
           (port DOUT1 (direction OUTPUT))
           (port DOUT2 (direction OUTPUT))
           (port DOUT3 (direction OUTPUT))
           (port DOUT4 (direction OUTPUT))
           (port DOUT5 (direction OUTPUT))
           (port DOUT6 (direction OUTPUT))
           (port DOUT7 (direction OUTPUT))
           (port DOUT8 (direction OUTPUT))
           (port DOUT9 (direction OUTPUT))
           (port DOUT10 (direction OUTPUT))
           (port DOUT11 (direction OUTPUT))
           (port DOUT12 (direction OUTPUT))
           (port DOUT13 (direction OUTPUT))
           (port DOUT14 (direction OUTPUT))
           (port DOUT15 (direction OUTPUT))
           (port DOUT16 (direction OUTPUT))
           (port DOUT17 (direction OUTPUT))
           (port DOUT18 (direction OUTPUT))
           (port DOUT19 (direction OUTPUT))
           (port DOUT20 (direction OUTPUT))
           (port DOUT21 (direction OUTPUT))
           (port DOUT22 (direction OUTPUT))
           (port DOUT23 (direction OUTPUT))
           (port DOUT24 (direction OUTPUT))
           (port DOUT25 (direction OUTPUT))
           (port DOUT26 (direction OUTPUT))
           (port DOUT27 (direction OUTPUT))
           (port DOUT28 (direction OUTPUT))
           (port DOUT29 (direction OUTPUT))
           (port DOUT30 (direction OUTPUT))
           (port DOUT31 (direction OUTPUT))
         )
         (contents
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          (instance (rename DOUT33 "DOUT_1_") (viewRef PRIM (cellref S_DFF (libraryRef ALTERA))))
          (instance (rename DOUT34 "DOUT_2_") (viewRef PRIM (cellref S_DFF (libraryRef ALTERA))))
          (instance (rename DOUT35 "DOUT_3_") (viewRef PRIM (cellref S_DFF (libraryRef ALTERA))))
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          (instance (rename DOUT39 "DOUT_7_") (viewRef PRIM (cellref S_DFF (libraryRef ALTERA))))
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          ))
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