freqtest.fit.eqn

基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯

F6L11_cout_1 = F6_safe_q[0];
F6L11 = CARRY(F6L11_cout_1);


--F7_safe_q[0] is CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated|safe_q[0] at LC_X27_Y12_N5
--operation mode is arithmetic

F7_safe_q[0]_lut_out = !F7_safe_q[0];
F7_safe_q[0]_reg_input = !D7L1 & F7_safe_q[0]_lut_out;
F7_safe_q[0] = DFFEA(F7_safe_q[0]_reg_input, D6L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F7L01 is CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated|safe_q[0]~COUT0 at LC_X27_Y12_N5
--operation mode is arithmetic

F7L01_cout_0 = F7_safe_q[0];
F7L01 = CARRY(F7L01_cout_0);

--F7L11 is CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated|safe_q[0]~COUT1 at LC_X27_Y12_N5
--operation mode is arithmetic

F7L11_cout_1 = F7_safe_q[0];
F7L11 = CARRY(F7L11_cout_1);


--F5_safe_q[0] is CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated|safe_q[0] at LC_X27_Y19_N6
--operation mode is arithmetic

F5_safe_q[0]_lut_out = !F5_safe_q[0];
F5_safe_q[0]_reg_input = !D5L1 & F5_safe_q[0]_lut_out;
F5_safe_q[0] = DFFEA(F5_safe_q[0]_reg_input, D4L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F5L01 is CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated|safe_q[0]~COUT0 at LC_X27_Y19_N6
--operation mode is arithmetic

F5L01_cout_0 = F5_safe_q[0];
F5L01 = CARRY(F5L01_cout_0);

--F5L11 is CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated|safe_q[0]~COUT1 at LC_X27_Y19_N6
--operation mode is arithmetic

F5L11_cout_1 = F5_safe_q[0];
F5L11 = CARRY(F5L11_cout_1);


--F8_safe_q[0] is CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[0] at LC_X26_Y15_N5
--operation mode is arithmetic

F8_safe_q[0]_lut_out = !F8_safe_q[0];
F8_safe_q[0]_reg_input = !D8L1 & F8_safe_q[0]_lut_out;
F8_safe_q[0] = DFFEA(F8_safe_q[0]_reg_input, D7L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F8L01 is CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[0]~COUT0 at LC_X26_Y15_N5
--operation mode is arithmetic

F8L01_cout_0 = F8_safe_q[0];
F8L01 = CARRY(F8L01_cout_0);

--F8L11 is CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[0]~COUT1 at LC_X26_Y15_N5
--operation mode is arithmetic

F8L11_cout_1 = F8_safe_q[0];
F8L11 = CARRY(F8L11_cout_1);


--F3_safe_q[0] is CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated|safe_q[0] at LC_X27_Y14_N5
--operation mode is arithmetic

F3_safe_q[0]_lut_out = !F3_safe_q[0];
F3_safe_q[0]_reg_input = !D3L1 & F3_safe_q[0]_lut_out;
F3_safe_q[0] = DFFEA(F3_safe_q[0]_reg_input, GLOBAL(D2L2), !B1_CLR_CNT, , B1_Div2CLK, , );

--F3L01 is CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated|safe_q[0]~COUT0 at LC_X27_Y14_N5
--operation mode is arithmetic

F3L01_cout_0 = F3_safe_q[0];
F3L01 = CARRY(F3L01_cout_0);

--F3L11 is CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated|safe_q[0]~COUT1 at LC_X27_Y14_N5
--operation mode is arithmetic

F3L11_cout_1 = F3_safe_q[0];
F3L11 = CARRY(F3L11_cout_1);


--F2_safe_q[0] is CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated|safe_q[0] at LC_X28_Y14_N0
--operation mode is arithmetic

F2_safe_q[0]_lut_out = !F2_safe_q[0];
F2_safe_q[0]_reg_input = !D2L1 & F2_safe_q[0]_lut_out;
F2_safe_q[0] = DFFEA(F2_safe_q[0]_reg_input, GLOBAL(D1L2), !B1_CLR_CNT, , B1_Div2CLK, , );

--F2L01 is CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated|safe_q[0]~COUT0 at LC_X28_Y14_N0
--operation mode is arithmetic

F2L01_cout_0 = F2_safe_q[0];
F2L01 = CARRY(F2L01_cout_0);

--F2L11 is CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated|safe_q[0]~COUT1 at LC_X28_Y14_N0
--operation mode is arithmetic

F2L11_cout_1 = F2_safe_q[0];
F2L11 = CARRY(F2L11_cout_1);


--F1_safe_q[0] is CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated|safe_q[0] at LC_X27_Y13_N5
--operation mode is arithmetic

F1_safe_q[0]_lut_out = !F1_safe_q[0];
F1_safe_q[0]_reg_input = !D1L1 & F1_safe_q[0]_lut_out;
F1_safe_q[0] = DFFEA(F1_safe_q[0]_reg_input, GLOBAL(FSIN), !B1_CLR_CNT, , B1_Div2CLK, , );

--F1L01 is CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated|safe_q[0]~COUT0 at LC_X27_Y13_N5
--operation mode is arithmetic

F1L01_cout_0 = F1_safe_q[0];
F1L01 = CARRY(F1L01_cout_0);

--F1L11 is CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated|safe_q[0]~COUT1 at LC_X27_Y13_N5
--operation mode is arithmetic

F1L11_cout_1 = F1_safe_q[0];
F1L11 = CARRY(F1L11_cout_1);


--F4_safe_q[0] is CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated|safe_q[0] at LC_X27_Y16_N0
--operation mode is arithmetic

F4_safe_q[0]_lut_out = !F4_safe_q[0];
F4_safe_q[0]_reg_input = !D4L1 & F4_safe_q[0]_lut_out;
F4_safe_q[0] = DFFEA(F4_safe_q[0]_reg_input, GLOBAL(D3L2), !B1_CLR_CNT, , B1_Div2CLK, , );

--F4L01 is CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated|safe_q[0]~COUT0 at LC_X27_Y16_N0
--operation mode is arithmetic

F4L01_cout_0 = F4_safe_q[0];
F4L01 = CARRY(F4L01_cout_0);

--F4L11 is CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated|safe_q[0]~COUT1 at LC_X27_Y16_N0
--operation mode is arithmetic

F4L11_cout_1 = F4_safe_q[0];
F4L11 = CARRY(F4L11_cout_1);


--A1L77 is Mux~189 at LC_X12_Y14_N0
--operation mode is normal

A1L77 = SEL[3] & !SEL[2];


--A1L85 is K3~61 at LC_X12_Y14_N1
--operation mode is normal

A1L85 = LCELL(A1L77 & (SEL[1] & !SEL[0] # !SEL[1] & A1L85));


--A1L65 is K2~61 at LC_X12_Y14_N8
--operation mode is normal

A1L65 = LCELL(A1L77 & (SEL[0] & !SEL[1] # !SEL[0] & A1L65));


--A1L06 is Mux~113 at LC_X13_Y14_N7
--operation mode is normal

A1L06 = !SEL[2] & SEL[3] & (SEL[1] $ SEL[0]);


--A1L45 is K1~46 at LC_X12_Y14_N3
--operation mode is normal

A1L45 = LCELL(A1L06 & A1L45 # !A1L06 & !SEL[0] & A1L77);


--D5L2 is CNT10:U7|reduce_nor~12 at LC_X27_Y19_N3
--operation mode is normal

D5L2 = !F5_safe_q[1] & !F5_safe_q[2] & F5_safe_q[3] & F5_safe_q[0];


--B1_CLR_CNT is TESTCTL:U1|CLR_CNT at LC_X27_Y12_N4
--operation mode is normal

B1_CLR_CNT = !CLK & !B1_Div2CLK;


--D6L1 is CNT10:U8|LessThan~14 at LC_X26_Y19_N4
--operation mode is normal

D6L1 = F6_safe_q[3] & (F6_safe_q[1] # F6_safe_q[0] # F6_safe_q[2]);


--D6L2 is CNT10:U8|reduce_nor~12 at LC_X26_Y19_N9
--operation mode is normal

D6L2 = !F6_safe_q[2] & F6_safe_q[0] & F6_safe_q[3] & !F6_safe_q[1];


--D7L1 is CNT10:U9|LessThan~14 at LC_X27_Y12_N1
--operation mode is normal

D7L1 = F7_safe_q[3] & (F7_safe_q[2] # F7_safe_q[0] # F7_safe_q[1]);


--D4L2 is CNT10:U6|reduce_nor~12 at LC_X27_Y16_N4
--operation mode is normal

D4L2 = !F4_safe_q[1] & F4_safe_q[3] & !F4_safe_q[2] & F4_safe_q[0];


--D5L1 is CNT10:U7|LessThan~14 at LC_X27_Y19_N4
--operation mode is normal

D5L1 = F5_safe_q[3] & (F5_safe_q[1] # F5_safe_q[2] # F5_safe_q[0]);


--D7L2 is CNT10:U9|reduce_nor~12 at LC_X27_Y12_N3
--operation mode is normal

D7L2 = !F7_safe_q[2] & F7_safe_q[0] & F7_safe_q[3] & !F7_safe_q[1];


--D8L1 is CNT10:U10|LessThan~14 at LC_X26_Y15_N1
--operation mode is normal

D8L1 = F8_safe_q[3] & (F8_safe_q[1] # F8_safe_q[2] # F8_safe_q[0]);


--D2L2 is CNT10:U4|reduce_nor~12 at LC_X28_Y14_N4
--operation mode is normal

D2L2 = !F2_safe_q[2] & F2_safe_q[0] & F2_safe_q[3] & !F2_safe_q[1];


--D3L1 is CNT10:U5|LessThan~14 at LC_X27_Y14_N4
--operation mode is normal

D3L1 = F3_safe_q[3] & (F3_safe_q[2] # F3_safe_q[0] # F3_safe_q[1]);


--D1L2 is CNT10:U3|reduce_nor~12 at LC_X27_Y13_N1
--operation mode is normal

D1L2 = !F1_safe_q[2] & F1_safe_q[0] & F1_safe_q[3] & !F1_safe_q[1];


--D2L1 is CNT10:U4|LessThan~14 at LC_X28_Y14_N6
--operation mode is normal

D2L1 = F2_safe_q[3] & (F2_safe_q[2] # F2_safe_q[0] # F2_safe_q[1]);


--D1L1 is CNT10:U3|LessThan~14 at LC_X27_Y13_N4
--operation mode is normal

D1L1 = F1_safe_q[3] & (F1_safe_q[2] # F1_safe_q[0] # F1_safe_q[1]);


--D3L2 is CNT10:U5|reduce_nor~12 at LC_X27_Y14_N9
--operation mode is normal

D3L2 = !F3_safe_q[2] & F3_safe_q[0] & F3_safe_q[3] & !F3_safe_q[1];


--D4L1 is CNT10:U6|LessThan~14 at LC_X27_Y16_N5
--operation mode is normal

D4L1 = F4_safe_q[3] & (F4_safe_q[2] # F4_safe_q[0] # F4_safe_q[1]);


--SEL[3] is SEL[3] at PIN_215
--operation mode is input

SEL[3] = INPUT();


--SEL[0] is SEL[0] at PIN_216
--operation mode is input

SEL[0] = INPUT();


--SEL[1] is SEL[1] at PIN_195
--operation mode is input

SEL[1] = INPUT();


--SEL[2] is SEL[2] at PIN_188
--operation mode is input

SEL[2] = INPUT();


--DIN[3] is DIN[3] at PIN_187
--operation mode is input

DIN[3] = INPUT();


--P37 is P37 at PIN_218
--operation mode is input

P37 = INPUT();


--DIN[2] is DIN[2] at PIN_186
--operation mode is input

DIN[2] = INPUT();


--DIN[1] is DIN[1] at PIN_185
--operation mode is input

DIN[1] = INPUT();


--DIN[0] is DIN[0] at PIN_184
--operation mode is input

DIN[0] = INPUT();


--CLK is CLK at PIN_153
--operation mode is input

CLK = INPUT();


--FSIN is FSIN at PIN_28
--operation mode is input

FSIN = INPUT();


--DLOW[3] is DLOW[3] at PIN_183
--operation mode is output

DLOW[3] = OUTPUT(A1L25);


--DLOW[2] is DLOW[2] at PIN_182
--operation mode is output

DLOW[2] = OUTPUT(A1L84);


--DLOW[1] is DLOW[1] at PIN_181
--operation mode is output

DLOW[1] = OUTPUT(A1L44);


--DLOW[0] is DLOW[0] at PIN_180
--operation mode is output

DLOW[0] = OUTPUT(A1L04);


--DATAOUT[11] is DATAOUT[11] at PIN_168
--operation mode is output

DATAOUT[11] = OUTPUT(DATA[11]);


--DATAOUT[10] is DATAOUT[10] at PIN_167
--operation mode is output

DATAOUT[10] = OUTPUT(DATA[10]);


--DATAOUT[9] is DATAOUT[9] at PIN_166
--operation mode is output

DATAOUT[9] = OUTPUT(DATA[9]);


--DATAOUT[8] is DATAOUT[8] at PIN_165
--operation mode is output

DATAOUT[8] = OUTPUT(DATA[8]);


--DATAOUT[7] is DATAOUT[7] at PIN_164
--operation mode is output

DATAOUT[7] = OUTPUT(DATA[7]);


--DATAOUT[6] is DATAOUT[6] at PIN_163
--operation mode is output

DATAOUT[6] = OUTPUT(DATA[6]);


--DATAOUT[5] is DATAOUT[5] at PIN_162
--operation mode is output

DATAOUT[5] = OUTPUT(DATA[5]);


--DATAOUT[4] is DATAOUT[4] at PIN_161
--operation mode is output

DATAOUT[4] = OUTPUT(DATA[4]);


--DATAOUT[3] is DATAOUT[3] at PIN_160
--operation mode is output

DATAOUT[3] = OUTPUT(DATA[3]);


--DATAOUT[2] is DATAOUT[2] at PIN_159
--operation mode is output

DATAOUT[2] = OUTPUT(DATA[2]);


--DATAOUT[1] is DATAOUT[1] at PIN_158
--operation mode is output

DATAOUT[1] = OUTPUT(DATA[1]);


--DATAOUT[0] is DATAOUT[0] at PIN_141
--operation mode is output

DATAOUT[0] = OUTPUT(DATA[0]);