freqtest.vhd

基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQTEST IS
    PORT ( CLK : IN STD_LOGIC;  --P43,CLOCK2
         FSIN : IN STD_LOGIC;  --P2 ,CLOCK0
         DLOW : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- P49,     48,47,39
                                                 --IO 27(P13),26,25,24(P10)
         DIN :  IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- P 53,     52,51,50
                                                 --IO 31(P17),30,29,28(P14)

         SEL  : IN STD_LOGIC_VECTOR(3 DOWNTO 0);    -- P 21      , 22      , 23
                                                    -- IO11(P32),IO12(P33),IO13(P34),IO14(P35)
          P37 : IN STD_LOGIC;                       -- P 25,      IO15(P37)
      DATAOUT : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)   -- P79,78,73,72,71,70,67,66,65,64,62,61
                                                    -- IO47-44,43-40,39-36
           );
END FREQTEST;
ARCHITECTURE struc OF FREQTEST IS
COMPONENT TESTCTL
    PORT ( CLK : IN STD_LOGIC;     TSTEN : OUT STD_LOGIC; 
       CLR_CNT : OUT STD_LOGIC;     Load : OUT STD_LOGIC   );
END COMPONENT;
COMPONENT CNT10
    PORT (    CLK : IN STD_LOGIC;  CLR : IN STD_LOGIC; ENA : IN STD_LOGIC;
               CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        CARRY_OUT : OUT STD_LOGIC );
END COMPONENT;
COMPONENT REG32B
    PORT (  Load : IN STD_LOGIC;
              DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
             DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END COMPONENT;
    SIGNAL TSTEN1 : STD_LOGIC;
    SIGNAL CLR_CNT1 : STD_LOGIC;
    SIGNAL Load1 : STD_LOGIC;
    SIGNAL DTO1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
    SIGNAL CARRY_OUT1 : STD_LOGIC_VECTOR(6 DOWNTO 0);
    SIGNAL  DOUT : STD_LOGIC_VECTOR(31 DOWNTO 0) ;
    SIGNAL SELL  : STD_LOGIC_VECTOR(3 DOWNTO 0);  
    SIGNAL  K1,K2,K3 : STD_LOGIC;
    SIGNAL  CLOCK1,CLOCK2,CLOCK3 : STD_LOGIC;

    SIGNAL      DATA : STD_LOGIC_VECTOR(11 DOWNTO 0); 
        
BEGIN
  U1 : TESTCTL  PORT MAP( CLK => CLK,    TSTEN => TSTEN1,  
                      CLR_CNT => CLR_CNT1, Load => Load1 );
  U2 : REG32B PORT MAP( Load => Load1, DIN => DTO1,DOUT => DOUT);
  U3 : CNT10  PORT MAP(CLK => FSIN,CLR => CLR_CNT1,ENA => TSTEN1,
        CQ => DTO1(3 DOWNTO 0),CARRY_OUT => CARRY_OUT1(0) );
  U4 : CNT10  PORT MAP(CLK => CARRY_OUT1(0), CLR => CLR_CNT1,
        ENA => TSTEN1, CQ => DTO1(7 DOWNTO 4), 
        CARRY_OUT => CARRY_OUT1(1)  );
  U5 : CNT10 PORT MAP( CLK => CARRY_OUT1(1), CLR => CLR_CNT1,
                      ENA => TSTEN1, CQ => DTO1(11 DOWNTO 8),
                CARRY_OUT => CARRY_OUT1(2) );
  U6 : CNT10 PORT MAP( CLK => CARRY_OUT1(2), CLR => CLR_CNT1,
        ENA => TSTEN1, CQ => DTO1(15 DOWNTO 12),
        CARRY_OUT => CARRY_OUT1(3));
  U7 : CNT10 PORT MAP( CLK => CARRY_OUT1(3), CLR => CLR_CNT1,
        ENA => TSTEN1,  CQ => DTO1(19 DOWNTO 16),
        CARRY_OUT => CARRY_OUT1(4) );
  U8 : CNT10   PORT MAP( CLK => CARRY_OUT1(4),CLR => CLR_CNT1,
           ENA => TSTEN1,  CQ => DTO1(23 DOWNTO 20),
           CARRY_OUT => CARRY_OUT1(5) );
  U9 : CNT10  PORT MAP( CLK => CARRY_OUT1(5),CLR => CLR_CNT1,
                   ENA => TSTEN1, CQ => DTO1(27 DOWNTO 24),
                   CARRY_OUT => CARRY_OUT1(6) );
  U10 : CNT10 PORT MAP( CLK => CARRY_OUT1(6),CLR => CLR_CNT1,
           ENA => TSTEN1, CQ => DTO1(31 DOWNTO 28) );
    SELL <=SEL(3) & SEL(2) & SEL(1) & SEL(0);
   
  Sch : PROCESS(SELL)
    BEGIN
        CASE SELL IS              -- 译码电路，查表方式，控制音调的预置数
            WHEN "0000"  => DLOW <= DOUT( 3 DOWNTO  0);K1 <='0'; K2 <='0'; K3 <='0'; 
            WHEN "0001"  => DLOW <= DOUT( 7 DOWNTO  4);K1 <='0'; K2 <='0'; K3 <='0'; 
            WHEN "0010"  => DLOW <= DOUT(11 DOWNTO  8);K1 <='0'; K2 <='0'; K3 <='0'; 
            WHEN "0011"  => DLOW <= DOUT(15 DOWNTO 12);K1 <='0'; K2 <='0'; K3 <='0'; 
            WHEN "0100"  => DLOW <= DOUT(19 DOWNTO 16);K1 <='0'; K2 <='0'; K3 <='0'; 
            WHEN "0101"  => DLOW <= DOUT(23 DOWNTO 20);K1 <='0'; K2 <='0'; K3 <='0'; 
            WHEN "0110"  => DLOW <= DOUT(27 DOWNTO 24);K1 <='0'; K2 <='0'; K3 <='0'; 
            WHEN "0111"  => DLOW <= DOUT(31 DOWNTO 28);K1 <='0'; K2 <='0'; K3 <='0'; 
          
            WHEN "1000"  =>  K1 <='1' ;  
            WHEN "1001"  =>  K2 <='1' ;  
            WHEN "1010"  =>  K3 <='1' ; 
            WHEN OTHERS => K1 <='0'; K2 <='0'; K3 <='0'; 
        END CASE;
    END PROCESS;

CLOCK1 <= K1 AND P37   ;
 CLOCK2 <= K2 AND P37 ;  
CLOCK3 <= K3 AND P37  ;
   
   
KK1: PROCESS(CLOCK1)
   BEGIN
   IF CLOCK1'EVENT AND CLOCK1 = '1' THEN    
          DATA( 3 DOWNTO 0) <= DIN;
        END IF;
    END PROCESS;

KK2: PROCESS(CLOCK2)
   BEGIN
   IF CLOCK2'EVENT AND CLOCK2 = '1' THEN    
          DATA( 7 DOWNTO 4) <= DIN;
        END IF;
    END PROCESS;

KK3: PROCESS(CLOCK3)
   BEGIN
   IF CLOCK3'EVENT AND CLOCK3 = '1' THEN    
          DATA( 11 DOWNTO 8) <= DIN;
        END IF;
    END PROCESS;
 
DATAOUT <= DATA ;

END struc;