adsuart.fit.summary

基于fpga和sopc的用VHDL语言编写的EDA信号采集与频谱分析电路

Flow Status : Successful - Tue Aug 02 13:56:18 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : ADSUART
Top-level Entity Name : adsuart
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Production
Total logic elements : 679 / 5,980 ( 11 % )
Total pins : 14 / 185 ( 7 % )
Total memory bits : 47,104 / 92,160 ( 51 % )
Total PLLs : 0 / 2 ( 0 % )