stp1.stp

基于fpga和sopc的用VHDL语言编写的EDA信号采集与频谱分析电路

          <wire connection_status="true" name="clk1" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[0]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[1]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[2]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[3]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[4]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[5]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[6]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[7]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="rxd" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="txd" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="xdata[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[5]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[6]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[7]" tap_mode="classic" type="register"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus link="all" name="d" order="msb_to_lsb" radix="line" state="collapse" type="input pin">
            <net name="d[7]"/>
            <net name="d[6]"/>
            <net name="d[5]"/>
            <net name="d[4]"/>
            <net name="d[3]"/>
            <net name="d[2]"/>
            <net name="d[1]"/>
            <net name="d[0]"/>
          </bus>