stp1.stp

基于fpga和sopc的用VHDL语言编写的EDA信号采集与频谱分析电路

<session jtag_chain="ByteBlasterMV [LPT1]" jtag_device="@1: EP1C3 (0x020810DD)" sof_file="ADSUART.sof">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="UART" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="UART" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="3"/>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2005/02/07 09:37:53  #0">
      <clock name="clk" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="yes" trigger_in_node="rst" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="clk1" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[0]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[1]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[2]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[3]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[4]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[5]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[6]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="d[7]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="rxd" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="txd" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="xdata[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[5]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[6]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="xdata[7]" tap_mode="classic" type="register"/>
        </trigger_input_vec>
        <data_input_vec>