reserv.fit.summary

基于fpga和sopc的用VHDL语言编写的EDA采样高速A/D的存储示波器

Flow Status : Successful - Sat Sep 17 10:15:49 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : RESERV
Top-level Entity Name : RESERV
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Production
Total logic elements : 508 / 5,980 ( 8 % )
Total pins : 32 / 185 ( 17 % )
Total memory bits : 45,056 / 92,160 ( 48 % )
Total PLLs : 0 / 2 ( 0 % )