reserv.map.rpt

基于fpga和sopc的用VHDL语言编写的EDA采样高速A/D的存储示波器

; Number of cells with combinational logic only          ; 159   ;
; Number of cells with registers only                    ; 179   ;
; Number of cells with combinational logic and registers ; 215   ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 15    ;
; Number of registers using Synchronous Load   ; 33    ;
; Number of registers using Asynchronous Clear ; 284   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 206   ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                          ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; Instance Index ; Instance Name ; Trigger Input Width ; Data Input Width ; Sample Depth ; Trigger Levels ; Advanced Trigger Levels ; Trigger In Used ; Trigger Out Used ; Incremental Trigger Inputs ; Incremental Data Inputs ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; 0              ; rsv1          ; 18                  ; 18               ; 2048         ; 1              ; 0                       ; yes             ; no               ; 0                          ; 0                       ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Setting                                                                                                     ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode       ; Hierarchy Location                                                              ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------------+
; 0              ; ramm        ; 8     ; 1024  ; Read/Write ; |RESERV|DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------------+


+-----------+
; Hierarchy ;
+-----------+
RESERV
 |-- lpm_counter:Q1_rtl_0
      |-- cntr_pt6:auto_generated
 |-- sld_signaltap:rsv1
      |-- sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst
           |-- lpm_counter:\adv_point_3_and_more:advance_pointer_counter
                |-- cntr_gv7:auto_generated
           |-- lpm_shiftreg:info_data_shift_out
           |-- lpm_shiftreg:ram_data_shift_out
           |-- lpm_counter:read_pointer_counter
                |-- cntr_ln7:auto_generated
      |-- altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram
           |-- altsyncram_aj82:auto_generated
      |-- sld_rom_sr:crc_rom_sr
      |-- sld_ela_control:ela_control
           |-- sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm
                |-- sld_mbpmg:\trigger_modules_gen:0:trigger_match
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1