etester.map.summary

来自「基于fpga和sopc的用VHDL语言编写的EDA等精度频率设计」· SUMMARY 代码 · 共 12 行

Flow Status : Successful - Tue May 10 16:31:21 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : ETESTER
Top-level Entity Name : etester
Family : Cyclone
Device : EP1C3T144C6
Timing Models : Production
Total logic elements : 123
Total pins : 18
Total memory bits : 0
Total PLLs : 0