etester.qws

来自「基于fpga和sopc的用VHDL语言编写的EDA等精度频率设计」· QWS 代码 · 共 39 行

[ProjectWorkspace]
ptn_Child1=Frames
ptn_Child2=Workmode
ptn_Child3=ActionPoints
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=ETESTER.VHD
DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
InCompileMode=True
InSimulateMode=False
InFirmwareMode=False
WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPJOPPPPPPFPPPPPPPCAAAAAAAIPCAAAAAOMBAAAAA
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
AFC_IN_REPORT=False
[ProjectWorkspace.Frames.ChildFrames.Document-1]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
DocPathName=../../../altera/quartus41/bin/Technology Viewer.qrui
DocumentCLSID={83708a55-a6bf-42c2-a7d6-2c58f5a106bb}
InCompileMode=True
InSimulateMode=False
InFirmwareMode=False
WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPJOPPPPPPKJAAAAAAKJAAAAAALADAAAAAHACAAAAA
IsActiveChildFrame=True
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
AFC_CMP_AP_NAME=ETESTER
AFC_PROJ_DB_PATH=D:/EDA_VHDL_Expt3/Chpt13_GWDVPB+/EP1C3_13_8_GWDVPB/db/ETESTER.quartus_db
[ProjectWorkspace.Workmode]
CurrentWorkmode=0