etester.map.rpt

基于fpga和sopc的用VHDL语言编写的EDA等精度频率设计

; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 64    ;
; Number of synthesis-generated cells                    ; 59    ;
; Number of WYSIWYG LUTs                                 ; 64    ;
; Number of synthesis-generated LUTs                     ; 58    ;
; Number of WYSIWYG registers                            ; 64    ;
; Number of synthesis-generated registers                ; 4     ;
; Number of cells with combinational logic only          ; 55    ;
; Number of cells with registers only                    ; 1     ;
; Number of cells with combinational logic and registers ; 67    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 68    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 64    ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
etester
 |-- lpm_counter:BZQ_rtl_0
      |-- cntr_b08:auto_generated
 |-- lpm_counter:TSQ_rtl_1
      |-- cntr_b08:auto_generated


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                               ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------+
; Compilation Hierarchy Node      ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                    ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------+
; |etester                        ; 123 (59)    ; 68           ; 0           ; 18   ; 0            ; 55 (55)      ; 1 (1)             ; 67 (3)           ; 64 (0)          ; |etester                                               ;
;    |lpm_counter:BZQ_rtl_0|      ; 32 (0)      ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (0)           ; 32 (0)          ; |etester|lpm_counter:BZQ_rtl_0                         ;
;       |cntr_b08:auto_generated| ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 32 (32)         ; |etester|lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated ;
;    |lpm_counter:TSQ_rtl_1|      ; 32 (0)      ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (0)           ; 32 (0)          ; |etester|lpm_counter:TSQ_rtl_1                         ;
;       |cntr_b08:auto_generated| ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 32 (32)         ; |etester|lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/EDA_VHDL_Expt3/Chapter13_B/EP1C3_13_8_GWDVPB/ETESTER.map.eqn.


+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                            ;
+-----------------------------------------------------------------+-----------------+
; File Name                                                       ; Used in Netlist ;
+-----------------------------------------------------------------+-----------------+
; ETESTER.VHD                                                     ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf     ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc    ; yes             ;
; E:/EDA_VHDL_Expt3/Chapter13_B/EP1C3_13_8_GWDVPB/db/cntr_b08.tdf ; yes             ;
+-----------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 123     ;
; Total combinational functions     ; 122     ;
; Total 4-input functions           ; 49      ;
; Total 3-input functions           ; 4       ;
; Total 2-input functions           ; 2       ;
; Total 1-input functions           ; 64      ;
; Total 0-input functions           ; 3       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 68      ;
; Total logic cells in carry chains ; 64      ;
; I/O pins                          ; 18      ;
; Maximum fan-out node              ; CLR     ;
; Maximum fan-out                   ; 68      ;
; Total fan-out                     ; 549     ;
; Average fan-out                   ; 3.89    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue May 10 16:31:14 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off ETESTER -c ETESTER
Info: Found 2 design units, including 1 entities, in source file ETESTER.VHD
    Info: Found design unit 1: etester-behav
    Info: Found entity 1: etester
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: BZQ[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: TSQ[0]~0
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_b08.tdf
    Info: Found entity 1: cntr_b08
Info: Implemented 141 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 10 output pins
    Info: Implemented 123 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue May 10 16:31:21 2005
    Info: Elapsed time: 00:00:06