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📄 etester.fit.rpt

📁 基于fpga和sopc的用VHDL语言编写的EDA等精度频率设计
💻 RPT
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;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella12 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella28 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella3  ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella19 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella11 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella27 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella2  ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella18 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella10 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella26 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella1  ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella17 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella9  ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella25 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella0  ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella16 ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella8  ; 1                 ; OFF     ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella24 ; 1                 ; OFF     ;
;      - CLK2                                                          ; 1                 ; OFF     ;
;      - MA~7                                                          ; 1                 ; OFF     ;
;      - ENA                                                           ; 1                 ; OFF     ;
; CLR                                                                  ;                   ;         ;
;      - Q2                                                            ; 0                 ; ON      ;
;      - Q3                                                            ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella15 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella23 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella7  ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella23 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella15 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella31 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella31 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella7  ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella14 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella22 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella6  ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella22 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella14 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella30 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella30 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella6  ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella13 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella21 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella5  ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella21 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella13 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella29 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella29 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella5  ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella12 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella20 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella4  ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella20 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella12 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella28 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella28 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella4  ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella11 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella19 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella3  ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella19 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella11 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella27 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella27 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella3  ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella10 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella18 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella2  ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella18 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella10 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella26 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella26 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella2  ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella9  ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella17 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella1  ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella17 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella9  ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella25 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella25 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella1  ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella8  ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella16 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella0  ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella16 ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella8  ; 0                 ; ON      ;
;      - lpm_counter:TSQ_rtl_1|cntr_b08:auto_generated|counter_cella24 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella24 ; 0                 ; ON      ;
;      - lpm_counter:BZQ_rtl_0|cntr_b08:auto_generated|counter_cella0  ; 0                 ; ON      ;
;      - Q1                                                            ; 0                 ; ON      ;
;      - ENA                                                           ; 0                 ; ON      ;
; BCLK                                                                 ;                   ;         ;
; SPUL                                                                 ;                   ;         ;
;      - ENA                                                           ; 0                 ; ON      ;
+----------------------------------------------------------------------+-------------------+---------+


+---------------------------------------------------------------------------------------------------+
; Control Signals                                                                                   ;
+---------+-------------+---------+--------------+--------+----------------------+------------------+
; Name    ; Location    ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ;
+---------+-------------+---------+--------------+--------+----------------------+------------------+
; BCLK    ; PIN_17      ; 32      ; Clock        ; yes    ; Global clock         ; GCLK3            ;
; BENA~23 ; LC_X2_Y9_N9 ; 32      ; Clock enable ; no     ; --                   ; --               ;
; CLK2    ; LC_X3_Y9_N8 ; 2       ; Clock        ; yes    ; Global clock         ; GCLK1            ;
; CLR     ; PIN_1       ; 68      ; Async. clear ; yes    ; Global clock         ; GCLK0            ;
; ENA     ; LC_X2_Y9_N9 ; 33      ; Clock enable ; no     ; --                   ; --               ;
; MA~7    ; LC_X3_Y9_N2 ; 1       ; Clock        ; no     ; --                   ; --               ;
; TCLK    ; PIN_39      ; 35      ; Clock        ; yes    ; Global clock         ; GCLK2            ;
+---------+-------------+---------+--------------+--------+----------------------+------------------+


+------------------------------------------------------------------------+
; Global & Other Fast Signals                                            ;
+------+-------------+---------+----------------------+------------------+
; Name ; Location    ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+-------------+---------+----------------------+------------------+
; BCLK ; PIN_17      ; 32      ; Global clock         ; GCLK3            ;
; CLK2 ; LC_X3_Y9_N8 ; 2       ; Global clock         ; GCLK1            ;
; CLR  ; PIN_1       ; 68      ; Global clock         ; GCLK0            ;
; TCLK ; PIN_39      ; 35      ; Global clock         ; GCLK2            ;
+------+-------------+---------+----------------------+------------------+


+------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                              ;
+--------------------------------------------------------------------+---------+
; Name                                                               ; Fan-Out ;
+--------------------------------------------------------------------+---------+
; ENA                                                                ; 33      ;
; BENA~23                                                            ; 32      ;
; SEL[0]                                                             ; 27      ;
; SEL[1]                                  

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