tennis.tan.rpt

基于fpga和sopc的用VHDL语言编写的EDA乒乓球游戏电路

; N/A           ; None             ; 17.725 ns      ; cou10:ubl|lpm_counter:qqout_rtl_3|cntr_2p7:auto_generated|safe_q[2] ; countbl[2] ; bbin       ;
; N/A           ; None             ; 17.731 ns      ; cou10:ubl|lpm_counter:qqout_rtl_3|cntr_2p7:auto_generated|safe_q[0] ; countbl[0] ; bbin       ;
; N/A           ; None             ; 17.955 ns      ; cou10:ubl|lpm_counter:qqout_rtl_3|cntr_2p7:auto_generated|safe_q[1] ; countbl[1] ; bbin       ;
; N/A           ; None             ; 18.562 ns      ; cou10:ual|lpm_counter:qqout_rtl_1|cntr_2p7:auto_generated|safe_q[2] ; countal[2] ; bain       ;
; N/A           ; None             ; 18.564 ns      ; cou10:ual|lpm_counter:qqout_rtl_1|cntr_2p7:auto_generated|safe_q[3] ; countal[3] ; bain       ;
; N/A           ; None             ; 18.979 ns      ; cou10:ual|lpm_counter:qqout_rtl_1|cntr_2p7:auto_generated|safe_q[0] ; countal[0] ; bain       ;
; N/A           ; None             ; 18.981 ns      ; cou10:ual|lpm_counter:qqout_rtl_1|cntr_2p7:auto_generated|safe_q[1] ; countal[1] ; bain       ;
; N/A           ; None             ; 21.111 ns      ; cou4:ubh|lpm_counter:qqout_rtl_2|cntr_2p7:auto_generated|safe_q[0]  ; countbh[0] ; bbin       ;
; N/A           ; None             ; 21.557 ns      ; cou4:ubh|lpm_counter:qqout_rtl_2|cntr_2p7:auto_generated|safe_q[2]  ; countbh[2] ; bbin       ;
; N/A           ; None             ; 21.557 ns      ; cou4:ubh|lpm_counter:qqout_rtl_2|cntr_2p7:auto_generated|safe_q[1]  ; countbh[1] ; bbin       ;
; N/A           ; None             ; 21.559 ns      ; cou4:ubh|lpm_counter:qqout_rtl_2|cntr_2p7:auto_generated|safe_q[3]  ; countbh[3] ; bbin       ;
; N/A           ; None             ; 23.846 ns      ; cou4:uah|lpm_counter:qqout_rtl_0|cntr_2p7:auto_generated|safe_q[1]  ; countah[1] ; bain       ;
; N/A           ; None             ; 24.154 ns      ; cou4:uah|lpm_counter:qqout_rtl_0|cntr_2p7:auto_generated|safe_q[0]  ; countah[0] ; bain       ;
; N/A           ; None             ; 25.714 ns      ; cou4:uah|lpm_counter:qqout_rtl_0|cntr_2p7:auto_generated|safe_q[2]  ; countah[2] ; bain       ;
; N/A           ; None             ; 25.942 ns      ; cou4:uah|lpm_counter:qqout_rtl_0|cntr_2p7:auto_generated|safe_q[3]  ; countah[3] ; bain       ;
+---------------+------------------+----------------+---------------------------------------------------------------------+------------+------------+


+------------------------------------------------------------------------+
; Minimum tpd                                                            ;
+---------------+-------------------+-----------------+--------+---------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From   ; To      ;
+---------------+-------------------+-----------------+--------+---------+
; N/A           ; None              ; 5.226 ns        ; clk    ; lamp    ;
; N/A           ; None              ; 11.092 ns       ; souclk ; speaker ;
; N/A           ; None              ; 13.222 ns       ; bbin   ; speaker ;
; N/A           ; None              ; 13.254 ns       ; bain   ; speaker ;
; N/A           ; None              ; 14.506 ns       ; clr    ; speaker ;
+---------------+-------------------+-----------------+--------+---------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Aug 02 08:18:47 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off TENNIS -c TENNIS --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
    Info: Assuming node bbin is an undefined clock
    Info: Assuming node bain is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock board:ubdb|couclk as buffer
    Info: Detected ripple clock cou10:ubl|cout as buffer
    Info: Detected ripple clock board:ubda|couclk as buffer
    Info: Detected ripple clock cou10:ual|cout as buffer
Info: Clock clk Internal fmax is restricted to 275.03 MHz between source register ball:uball|lamp[5] and destination register ball:uball|lamp[6]
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.285 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y18_N6; Fanout = 7; REG Node = 'ball:uball|lamp[5]'
            Info: 2: + IC(0.547 ns) + CELL(0.738 ns) = 1.285 ns; Loc. = LC_X1_Y18_N9; Fanout = 3; REG Node = 'ball:uball|lamp[6]'
            Info: Total cell delay = 0.738 ns ( 57.43 % )
            Info: Total interconnect delay = 0.547 ns ( 42.57 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 2.931 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 11; CLK Node = 'clk'
                Info: 2: + IC(0.751 ns) + CELL(0.711 ns) = 2.931 ns; Loc. = LC_X1_Y18_N9; Fanout = 3; REG Node = 'ball:uball|lamp[6]'
                Info: Total cell delay = 2.180 ns ( 74.38 % )
                Info: Total interconnect delay = 0.751 ns ( 25.62 % )
            Info: - Longest clock path from clock clk to source register is 2.931 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 11; CLK Node = 'clk'
                Info: 2: + IC(0.751 ns) + CELL(0.711 ns) = 2.931 ns; Loc. = LC_X1_Y18_N6; Fanout = 7; REG Node = 'ball:uball|lamp[5]'
                Info: Total cell delay = 2.180 ns ( 74.38 % )
                Info: Total interconnect delay = 0.751 ns ( 25.62 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock bbin Internal fmax is restricted to 275.03 MHz between source register board:ubdb|serclk and destination register board:ubdb|couclk
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.090 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y17_N4; Fanout = 2; REG Node = 'board:ubdb|serclk'
            Info: 2: + IC(0.766 ns) + CELL(0.114 ns) = 0.880 ns; Loc. = LC_X6_Y17_N0; Fanout = 2; COMB Node = 'ballctrl:ucpu|ballen~168'
            Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.176 ns; Loc. = LC_X6_Y17_N1; Fanout = 3; COMB Node = 'ballctrl:ucpu|serve~143'
            Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 1.472 ns; Loc. = LC_X6_Y17_N2; Fanout = 2; COMB Node = 'board:ubdb|couclk~1'
            Info: 5: + IC(0.751 ns) + CELL(0.867 ns) = 3.090 ns; Loc. = LC_X7_Y17_N7; Fanout = 5; REG Node = 'board:ubdb|couclk'
            Info: Total cell delay = 1.209 ns ( 39.13 % )
            Info: Total interconnect delay = 1.881 ns ( 60.87 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock bbin to destination register is 7.067 ns
                Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_233; Fanout = 5; CLK Node = 'bbin'
                Info: 2: + IC(4.881 ns) + CELL(0.711 ns) = 7.067 ns; Loc. = LC_X7_Y17_N7; Fanout = 5; REG Node = 'board:ubdb|couclk'
                Info: Total cell delay = 2.186 ns ( 30.93 % )
                Info: Total interconnect delay = 4.881 ns ( 69.07 % )
            Info: - Longest clock path from clock bbin to source register is 7.067 ns
                Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_233; Fanout = 5; CLK Node = 'bbin'
                Info: 2: + IC(4.881 ns) + CELL(0.711 ns) = 7.067 ns; Loc. = LC_X7_Y17_N4; Fanout = 2; REG Node = 'board:ubdb|serclk'
                Info: Total cell delay = 2.186 ns ( 30.93 % )
                Info: Total interconnect delay = 4.881 ns ( 69.07 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock bain Internal fmax is restricted to 275.03 MHz between source register board:ubda|serclk and destination register board:ubda|couclk
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.040 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y17_N7; Fanout = 2; REG Node = 'board:ubda|serclk'
            Info: 2: + IC(0.553 ns) + CELL(0.292 ns) = 0.845 ns; Loc. = LC_X6_Y17_N0; Fanout = 2; COMB Node = 'ball