multi8x8.fit.eqn

基于fpga和sopc的用VHDL语言编写的EDA移位相加硬件乘法器

--F1_R16S[15] is REG16B:U5|R16S[15] at LC_X10_Y11_N9
--operation mode is normal

F1_R16S[15]_carry_eqn = (!F1L01 & F1L04) # (F1L01 & F1L14);
F1_R16S[15]_lut_out = F1_R16S[15]_carry_eqn;
F1_R16S[15] = DFFEA(F1_R16S[15]_lut_out, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );


--F1_R16S[14] is REG16B:U5|R16S[14] at LC_X10_Y11_N8
--operation mode is arithmetic

F1_R16S[14]_carry_eqn = (!F1L01 & F1L63) # (F1L01 & F1L73);
F1_R16S[14]_lut_out = F1_R16S[15] $ D1_DOUT[7] $ !F1_R16S[14]_carry_eqn;
F1_R16S[14] = DFFEA(F1_R16S[14]_lut_out, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );

--F1L04 is REG16B:U5|R16S[14]~COUT0 at LC_X10_Y11_N8
--operation mode is arithmetic

F1L04_cout_0 = F1_R16S[15] & (D1_DOUT[7] # !F1L63) # !F1_R16S[15] & D1_DOUT[7] & !F1L63;
F1L04 = CARRY(F1L04_cout_0);

--F1L14 is REG16B:U5|R16S[14]~COUT1 at LC_X10_Y11_N8
--operation mode is arithmetic

F1L14_cout_1 = F1_R16S[15] & (D1_DOUT[7] # !F1L73) # !F1_R16S[15] & D1_DOUT[7] & !F1L73;
F1L14 = CARRY(F1L14_cout_1);


--F1_R16S[13] is REG16B:U5|R16S[13] at LC_X10_Y11_N7
--operation mode is arithmetic

F1_R16S[13]_carry_eqn = (!F1L01 & F1L23) # (F1L01 & F1L33);
F1_R16S[13]_lut_out = D1_DOUT[6] $ F1_R16S[14] $ F1_R16S[13]_carry_eqn;
F1_R16S[13] = DFFEA(F1_R16S[13]_lut_out, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );

--F1L63 is REG16B:U5|R16S[13]~COUT0 at LC_X10_Y11_N7
--operation mode is arithmetic

F1L63_cout_0 = D1_DOUT[6] & !F1_R16S[14] & !F1L23 # !D1_DOUT[6] & (!F1L23 # !F1_R16S[14]);
F1L63 = CARRY(F1L63_cout_0);

--F1L73 is REG16B:U5|R16S[13]~COUT1 at LC_X10_Y11_N7
--operation mode is arithmetic

F1L73_cout_1 = D1_DOUT[6] & !F1_R16S[14] & !F1L33 # !D1_DOUT[6] & (!F1L33 # !F1_R16S[14]);
F1L73 = CARRY(F1L73_cout_1);


--F1_R16S[12] is REG16B:U5|R16S[12] at LC_X10_Y11_N6
--operation mode is arithmetic

F1_R16S[12]_carry_eqn = (!F1L01 & F1L82) # (F1L01 & F1L92);
F1_R16S[12]_lut_out = F1_R16S[13] $ D1_DOUT[5] $ !F1_R16S[12]_carry_eqn;
F1_R16S[12] = DFFEA(F1_R16S[12]_lut_out, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );

--F1L23 is REG16B:U5|R16S[12]~COUT0 at LC_X10_Y11_N6
--operation mode is arithmetic

F1L23_cout_0 = F1_R16S[13] & (D1_DOUT[5] # !F1L82) # !F1_R16S[13] & D1_DOUT[5] & !F1L82;
F1L23 = CARRY(F1L23_cout_0);

--F1L33 is REG16B:U5|R16S[12]~COUT1 at LC_X10_Y11_N6
--operation mode is arithmetic

F1L33_cout_1 = F1_R16S[13] & (D1_DOUT[5] # !F1L92) # !F1_R16S[13] & D1_DOUT[5] & !F1L92;
F1L33 = CARRY(F1L33_cout_1);


--F1_R16S[11] is REG16B:U5|R16S[11] at LC_X10_Y11_N5
--operation mode is arithmetic

F1_R16S[11]_carry_eqn = F1L01;
F1_R16S[11]_lut_out = F1_R16S[12] $ D1_DOUT[4] $ F1_R16S[11]_carry_eqn;
F1_R16S[11] = DFFEA(F1_R16S[11]_lut_out, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );

--F1L82 is REG16B:U5|R16S[11]~COUT0 at LC_X10_Y11_N5
--operation mode is arithmetic

F1L82_cout_0 = F1_R16S[12] & !D1_DOUT[4] & !F1L01 # !F1_R16S[12] & (!F1L01 # !D1_DOUT[4]);
F1L82 = CARRY(F1L82_cout_0);

--F1L92 is REG16B:U5|R16S[11]~COUT1 at LC_X10_Y11_N5
--operation mode is arithmetic

F1L92_cout_1 = F1_R16S[12] & !D1_DOUT[4] & !F1L01 # !F1_R16S[12] & (!F1L01 # !D1_DOUT[4]);
F1L92 = CARRY(F1L92_cout_1);


--F1_R16S[10] is REG16B:U5|R16S[10] at LC_X10_Y11_N3
--operation mode is arithmetic

F1_R16S[10]_lut_out = F1_R16S[11] $ D1_DOUT[3] $ F1L02;
F1_R16S[10] = DFFEA(F1_R16S[10]_lut_out, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );

--F1L42 is REG16B:U5|R16S[10]~COUT0 at LC_X10_Y11_N3
--operation mode is arithmetic

F1L42_cout_0 = F1_R16S[11] & !D1_DOUT[3] & !F1L02 # !F1_R16S[11] & (!F1L02 # !D1_DOUT[3]);
F1L42 = CARRY(F1L42_cout_0);

--F1L52 is REG16B:U5|R16S[10]~COUT1 at LC_X10_Y11_N3
--operation mode is arithmetic

F1L52_cout_1 = F1_R16S[11] & !D1_DOUT[3] & !F1L12 # !F1_R16S[11] & (!F1L12 # !D1_DOUT[3]);
F1L52 = CARRY(F1L52_cout_1);


--F1_R16S[9] is REG16B:U5|R16S[9] at LC_X10_Y11_N2
--operation mode is arithmetic

F1_R16S[9]_lut_out = D1_DOUT[2] $ F1_R16S[10] $ !F1L61;
F1_R16S[9] = DFFEA(F1_R16S[9]_lut_out, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );

--F1L02 is REG16B:U5|R16S[9]~COUT0 at LC_X10_Y11_N2
--operation mode is arithmetic

F1L02_cout_0 = D1_DOUT[2] & (F1_R16S[10] # !F1L61) # !D1_DOUT[2] & F1_R16S[10] & !F1L61;
F1L02 = CARRY(F1L02_cout_0);

--F1L12 is REG16B:U5|R16S[9]~COUT1 at LC_X10_Y11_N2
--operation mode is arithmetic

F1L12_cout_1 = D1_DOUT[2] & (F1_R16S[10] # !F1L71) # !D1_DOUT[2] & F1_R16S[10] & !F1L71;
F1L12 = CARRY(F1L12_cout_1);


--F1_R16S[8] is REG16B:U5|R16S[8] at LC_X10_Y11_N1
--operation mode is arithmetic

F1_R16S[8]_lut_out = F1_R16S[9] $ D1_DOUT[1] $ F1L21;
F1_R16S[8] = DFFEA(F1_R16S[8]_lut_out, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );

--F1L61 is REG16B:U5|R16S[8]~COUT0 at LC_X10_Y11_N1
--operation mode is arithmetic

F1L61_cout_0 = F1_R16S[9] & !D1_DOUT[1] & !F1L21 # !F1_R16S[9] & (!F1L21 # !D1_DOUT[1]);
F1L61 = CARRY(F1L61_cout_0);

--F1L71 is REG16B:U5|R16S[8]~COUT1 at LC_X10_Y11_N1
--operation mode is arithmetic

F1L71_cout_1 = F1_R16S[9] & !D1_DOUT[1] & !F1L31 # !F1_R16S[9] & (!F1L31 # !D1_DOUT[1]);
F1L71 = CARRY(F1L71_cout_1);


--F1_R16S[7] is REG16B:U5|R16S[7] at LC_X10_Y11_N0
--operation mode is arithmetic

F1_R16S[7]_lut_out = F1_R16S[8] $ D1_DOUT[0];
F1_R16S[7] = DFFEA(F1_R16S[7]_lut_out, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );

--F1L21 is REG16B:U5|R16S[7]~COUT0 at LC_X10_Y11_N0
--operation mode is arithmetic

F1L21_cout_0 = F1_R16S[8] & D1_DOUT[0];
F1L21 = CARRY(F1L21_cout_0);

--F1L31 is REG16B:U5|R16S[7]~COUT1 at LC_X10_Y11_N0
--operation mode is arithmetic

F1L31_cout_1 = F1_R16S[8] & D1_DOUT[0];
F1L31 = CARRY(F1L31_cout_1);


--F1_R16S[6] is REG16B:U5|R16S[6] at LC_X1_Y14_N9
--operation mode is normal

F1_R16S[6]_sload_eqn = F1_R16S[7];
F1_R16S[6] = DFFEA(F1_R16S[6]_sload_eqn, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );


--F1_R16S[5] is REG16B:U5|R16S[5] at LC_X1_Y14_N5
--operation mode is normal

F1_R16S[5]_sload_eqn = F1_R16S[6];
F1_R16S[5] = DFFEA(F1_R16S[5]_sload_eqn, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );


--F1_R16S[4] is REG16B:U5|R16S[4] at LC_X1_Y14_N2
--operation mode is normal

F1_R16S[4]_lut_out = F1_R16S[5];
F1_R16S[4] = DFFEA(F1_R16S[4]_lut_out, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );


--F1_R16S[3] is REG16B:U5|R16S[3] at LC_X1_Y14_N7
--operation mode is normal

F1_R16S[3]_sload_eqn = F1_R16S[4];
F1_R16S[3] = DFFEA(F1_R16S[3]_sload_eqn, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );


--F1_R16S[2] is REG16B:U5|R16S[2] at LC_X1_Y14_N8
--operation mode is normal

F1_R16S[2]_sload_eqn = F1_R16S[3];
F1_R16S[2] = DFFEA(F1_R16S[2]_sload_eqn, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );


--F1_R16S[1] is REG16B:U5|R16S[1] at LC_X1_Y14_N4
--operation mode is normal

F1_R16S[1]_sload_eqn = F1_R16S[2];
F1_R16S[1] = DFFEA(F1_R16S[1]_sload_eqn, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );


--F1_R16S[0] is REG16B:U5|R16S[0] at LC_X1_Y14_N6
--operation mode is normal

F1_R16S[0]_sload_eqn = F1_R16S[1];
F1_R16S[0] = DFFEA(F1_R16S[0]_sload_eqn, GLOBAL(B1L1), !GLOBAL(A1L73), , , , );


--H1_safe_q[3] is ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated|safe_q[3] at LC_X7_Y14_N8
--operation mode is normal

H1_safe_q[3]_lut_out = H1_safe_q[3] $ H1L61;
H1_safe_q[3] = DFFEA(H1_safe_q[3]_lut_out, GLOBAL(CLKK), !GLOBAL(A1L73), , !H1_safe_q[3], , );


--B1L1 is ARICTL:U1|CLKOUT~24 at LC_X7_Y14_N2
--operation mode is normal

B1L1 = CLKK & (A1L73 # !H1_safe_q[3]);


--C1_REG8[0] is SREG8B:U2|REG8[0] at LC_X9_Y11_N1
--operation mode is normal

C1_REG8[0]_lut_out = B[0] & (A1L73 # C1_REG8[1]) # !B[0] & !A1L73 & C1_REG8[1];
C1_REG8[0] = DFFEA(C1_REG8[0]_lut_out, GLOBAL(B1L1), VCC, , , , );


--D1_DOUT[7] is ANDARITH:U3|DOUT[7] at LC_X9_Y11_N9
--operation mode is normal

D1_DOUT[7] = A[7] & C1_REG8[0];


--D1_DOUT[6] is ANDARITH:U3|DOUT[6] at LC_X9_Y11_N6
--operation mode is normal

D1_DOUT[6] = A[6] & C1_REG8[0];


--D1_DOUT[5] is ANDARITH:U3|DOUT[5] at LC_X9_Y11_N2
--operation mode is normal

D1_DOUT[5] = A[5] & C1_REG8[0];


--D1_DOUT[4] is ANDARITH:U3|DOUT[4] at LC_X9_Y11_N0
--operation mode is normal

D1_DOUT[4] = A[4] & C1_REG8[0];


--F1L01 is REG16B:U5|R16S[7]~0 at LC_X10_Y11_N4
--operation mode is arithmetic

F1L01 = CARRY(!F1L52);


--D1_DOUT[3] is ANDARITH:U3|DOUT[3] at LC_X9_Y11_N5
--operation mode is normal

D1_DOUT[3] = A[3] & C1_REG8[0];


--D1_DOUT[2] is ANDARITH:U3|DOUT[2] at LC_X9_Y11_N8
--operation mode is normal

D1_DOUT[2] = A[2] & C1_REG8[0];


--D1_DOUT[1] is ANDARITH:U3|DOUT[1] at LC_X9_Y11_N7
--operation mode is normal

D1_DOUT[1] = A[1] & C1_REG8[0];


--D1_DOUT[0] is ANDARITH:U3|DOUT[0] at LC_X9_Y11_N4
--operation mode is normal

D1_DOUT[0] = A[0] & C1_REG8[0];


--A1L73 is NEWSTART~33 at LC_X10_Y14_N2
--operation mode is normal

A1L73 = LCELL(START # A1L73 & CLKK);


--H1_safe_q[2] is ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated|safe_q[2] at LC_X7_Y14_N7
--operation mode is arithmetic

H1_safe_q[2]_lut_out = H1_safe_q[2] $ !H1L31;
H1_safe_q[2] = DFFEA(H1_safe_q[2]_lut_out, GLOBAL(CLKK), !GLOBAL(A1L73), , !H1_safe_q[3], , );

--H1L61 is ARICTL:U1|lpm_counter:CNT4B_rtl_0|cntr_qu7:auto_generated|safe_q[2]~COUT0 at LC_X7_Y14_N7
--operation mode is arithmetic

H1L61_cout_0 = H1_safe_q[2] & !H1L31;