multi8x8.tan.summary

来自「基于fpga和sopc的用VHDL语言编写的EDA移位相加硬件乘法器」· SUMMARY 代码 · 共 87 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.333 ns
From           : A[5]
To             : REG16B:U5|R16S[15]
From Clock     : 
To Clock       : CLKK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.461 ns
From           : REG16B:U5|R16S[11]
To             : DOUT[11]
From Clock     : START
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 5.922 ns
From           : CLKK
To             : SREG8B:U2|REG8[0]
From Clock     : 
To Clock       : START
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.715 ns
From           : REG16B:U5|R16S[6]
To             : DOUT[6]
From Clock     : CLKK
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'CLKK'
Slack          : N/A
Required Time  : None
Actual Time    : 198.61 MHz ( period = 5.035 ns )
From           : SREG8B:U2|REG8[0]
To             : REG16B:U5|R16S[15]
From Clock     : CLKK
To Clock       : CLKK
Failed Paths   : 0

Type           : Clock Setup: 'START'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : SREG8B:U2|REG8[0]
To             : REG16B:U5|R16S[15]
From Clock     : START
To Clock       : START
Failed Paths   : 0

Type           : Clock Hold: 'CLKK'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : REG16B:U5|R16S[2]
To             : REG16B:U5|R16S[1]
From Clock     : CLKK
To Clock       : CLKK
Failed Paths   : 19

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 19

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