adder4b.vhd

来自「基于fpga和sopc的用VHDL语言编写的EDA移位相加硬件乘法器」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ADDER4B IS
    PORT (
        CIN : IN STD_LOGIC;
        A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        COUT : OUT STD_LOGIC
    );
END ADDER4B;

ARCHITECTURE behav OF ADDER4B IS
    SIGNAL SINT : STD_LOGIC_VECTOR(4 DOWNTO 0);
	SIGNAL AA,BB : STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
	AA<='0'&A;
	BB<='0'&B;
    SINT <= AA + BB + CIN;
    S <= SINT(3 DOWNTO 0);
    COUT <= SINT(4);
END behav;