resv.fit.eqn

基于fpga和sopc的用VHDL语言编写的EDA数据采集电路和简易存储示波器

--B1_REGL[3] is ADCINT:inst|REGL[3] at LC_X19_Y9_N2
--operation mode is normal

B1_REGL[3]_sload_eqn = D[3];
B1_REGL[3] = DFFEA(B1_REGL[3]_sload_eqn, GLOBAL(B1L5Q), VCC, , , , );


--J1_ram_rom_data_reg[3] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] at LC_X14_Y7_N6
--operation mode is normal

J1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L7, J1_ram_rom_data_reg[3], J1L01, H1_q_b[3], J1_ram_rom_data_reg[4], VCC, J1L9);


--B1_REGL[2] is ADCINT:inst|REGL[2] at LC_X19_Y13_N2
--operation mode is normal

B1_REGL[2]_sload_eqn = D[2];
B1_REGL[2] = DFFEA(B1_REGL[2]_sload_eqn, GLOBAL(B1L5Q), VCC, , , , );


--J1_ram_rom_data_reg[2] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] at LC_X14_Y7_N8
--operation mode is normal

J1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L7, J1_ram_rom_data_reg[2], J1L01, H1_q_b[2], J1_ram_rom_data_reg[3], VCC, J1L9);


--B1_REGL[1] is ADCINT:inst|REGL[1] at LC_X15_Y10_N2
--operation mode is normal

B1_REGL[1]_sload_eqn = D[1];
B1_REGL[1] = DFFEA(B1_REGL[1]_sload_eqn, GLOBAL(B1L5Q), VCC, , , , );


--J1_ram_rom_data_reg[1] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] at LC_X14_Y7_N0
--operation mode is normal

J1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L7, J1_ram_rom_data_reg[2], J1L01, H1_q_b[1], J1_ram_rom_data_reg[1], VCC, J1L9);


--B1_REGL[0] is ADCINT:inst|REGL[0] at LC_X14_Y13_N2
--operation mode is normal

B1_REGL[0]_sload_eqn = D[0];
B1_REGL[0] = DFFEA(B1_REGL[0]_sload_eqn, GLOBAL(B1L5Q), VCC, , , , );


--J1_ram_rom_data_reg[0] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] at LC_X14_Y7_N7
--operation mode is normal

J1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L7, J1_ram_rom_data_reg[0], J1L01, H1_q_b[0], J1_ram_rom_data_reg[1], VCC, J1L9);


--E1L51Q is sld_hub:sld_hub_inst|HUB_TDO~reg0 at LC_X14_Y8_N3
--operation mode is normal

E1L51Q = AMPP_FUNCTION(!A1L7, E1_jtag_debug_mode_usr1, Q6_Q[0], E1L31, E1L11, !T1_state[8], E1L92);


--N1_safe_q[3] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[3] at LC_X13_Y7_N8
--operation mode is normal

N1_safe_q[3] = AMPP_FUNCTION(A1L7, N1_safe_q[3], J1L01, !Q1_Q[3], J1_ram_rom_load_read_data, N1L61, N1L71);


--N1_safe_q[1] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[1] at LC_X13_Y7_N6
--operation mode is arithmetic

N1_safe_q[1] = AMPP_FUNCTION(A1L7, N1_safe_q[1], J1L01, !Q1_Q[3], J1_ram_rom_load_read_data, N1L01, N1L11);

--N1L31 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[1]~COUT0 at LC_X13_Y7_N6
--operation mode is arithmetic

N1L31 = AMPP_FUNCTION(N1_safe_q[1], N1L01);

--N1L41 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[1]~COUT1 at LC_X13_Y7_N6
--operation mode is arithmetic

N1L41 = AMPP_FUNCTION(N1_safe_q[1], N1L11);


--N1_safe_q[0] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[0] at LC_X13_Y7_N5
--operation mode is arithmetic

N1_safe_q[0] = AMPP_FUNCTION(A1L7, N1_safe_q[0], J1L01, !Q1_Q[3], J1_ram_rom_load_read_data);

--N1L01 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[0]~COUT0 at LC_X13_Y7_N5
--operation mode is arithmetic

N1L01 = AMPP_FUNCTION(N1_safe_q[0]);

--N1L11 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[0]~COUT1 at LC_X13_Y7_N5
--operation mode is arithmetic

N1L11 = AMPP_FUNCTION(N1_safe_q[0]);


--N1_safe_q[2] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[2] at LC_X13_Y7_N7
--operation mode is arithmetic

N1_safe_q[2] = AMPP_FUNCTION(A1L7, N1_safe_q[2], J1L01, !Q1_Q[3], J1_ram_rom_load_read_data, N1L31, N1L41);

--N1L61 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[2]~COUT0 at LC_X13_Y7_N7
--operation mode is arithmetic

N1L61 = AMPP_FUNCTION(N1_safe_q[2], N1L31);

--N1L71 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[2]~COUT1 at LC_X13_Y7_N7
--operation mode is arithmetic

N1L71 = AMPP_FUNCTION(N1_safe_q[2], N1L41);


--J1_ram_rom_load_read_data is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_load_read_data at LC_X13_Y7_N0
--operation mode is normal

J1_ram_rom_load_read_data = AMPP_FUNCTION(N1_safe_q[2], N1_safe_q[0], N1_safe_q[3], N1_safe_q[1]);


--Q2_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2] at LC_X15_Y9_N4
--operation mode is normal

Q2_Q[2] = AMPP_FUNCTION(A1L7, Q6_Q[2], !E1L2, GND, E1L8);


--Q6_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] at LC_X11_Y9_N2
--operation mode is normal

Q6_Q[2] = AMPP_FUNCTION(A1L7, Q6_Q[2], J1_ir_loaded_address_reg[1], Q6_Q[3], E1L61, !E1L2, T1_state[4], E1_IRSR_ENA);


--T1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] at LC_X11_Y10_N9
--operation mode is normal

T1_state[1] = AMPP_FUNCTION(A1L7, T1_state[0], T1L81, A1L9, VCC);


--E1L2 is sld_hub:sld_hub_inst|CLEAR_SIGNAL~0 at LC_X11_Y10_N0
--operation mode is normal

E1L2 = AMPP_FUNCTION(T1_state[1]);

--Q7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] at LC_X11_Y10_N0
--operation mode is normal

Q7_Q[0] = AMPP_FUNCTION(A1L7, U1_dffe1a[7], E1_jtag_debug_mode_usr1, GND, E1L3);


--Q5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] at LC_X10_Y9_N4
--operation mode is normal

Q5_Q[0] = AMPP_FUNCTION(A1L7, altera_internal_jtag, VCC, E1L71);


--U1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[2] at LC_X11_Y8_N0
--operation mode is normal

U1_dffe1a[2] = AMPP_FUNCTION(A1L7, E1L42, Q6_Q[3], Q6_Q[1], Q6_Q[2], !E1L2, E1L7);


--E1L81 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~76 at LC_X14_Y9_N1
--operation mode is normal

E1L81 = AMPP_FUNCTION(Q3_Q[0], Q4_Q[0], Q5_Q[0], U1_dffe1a[2]);


--T1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] at LC_X13_Y9_N5
--operation mode is normal

T1_state[5] = AMPP_FUNCTION(A1L7, T1_state[4], A1L9, T1_state[3], VCC);


--E1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q at LC_X16_Y8_N2
--operation mode is normal

E1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L7, T1_state[8], E1_jtag_debug_mode_usr1, VCC, E1L82);


--E1L91 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~77 at LC_X14_Y9_N2
--operation mode is normal

E1L91 = AMPP_FUNCTION(T1_state[5], E1_OK_TO_UPDATE_IR_Q, E1L81);


--E1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode at LC_X15_Y8_N3
--operation mode is normal

E1_jtag_debug_mode = AMPP_FUNCTION(A1L7, E1L42, T1_state[15], E1L52, E1_jtag_debug_mode, T1_state[0]);


--E1L62 is sld_hub:sld_hub_inst|NODE_ENA~1 at LC_X13_Y8_N0
--operation mode is normal

E1L62 = AMPP_FUNCTION(Q4_Q[0], E1_jtag_debug_mode);

--Q3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] at LC_X13_Y8_N0
--operation mode is normal

Q3_Q[0] = AMPP_FUNCTION(A1L7, U1_dffe1a[1], !E1L2, GND, E1L1);


--T1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] at LC_X10_Y8_N9
--operation mode is normal

T1_state[4] = AMPP_FUNCTION(A1L7, T1_state[4], A1L9, T1_state[3], T1_state[7], VCC);


--E1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X11_Y8_N8
--operation mode is normal

E1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L7, S1_dffs[0], E1L03, E1L13, S1_dffs[1], T1_state[0], T1_state[12]);


--Q1_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] at LC_X14_Y7_N1
--operation mode is normal

Q1_Q[1] = AMPP_FUNCTION(A1L7, Q3_Q[0], Q6_Q[1], Q2_Q[1], !E1L2, E1L91);


--E1L21 is sld_hub:sld_hub_inst|HUB_TDO~341 at LC_X14_Y7_N3
--operation mode is normal

E1L21 = AMPP_FUNCTION(Q1_Q[2], Q1_Q[1]);


--J1L01 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~55 at LC_X14_Y7_N4
--operation mode is normal

J1L01 = AMPP_FUNCTION(T1_state[4], E1L62, E1_jtag_debug_mode_usr1, E1L21);


--Q1_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] at LC_X14_Y9_N0
--operation mode is normal