resv.fit.eqn

基于fpga和sopc的用VHDL语言编写的EDA数据采集电路和简易存储示波器

P1_safe_q[5] = DFFEA(P1_safe_q[5]_lut_out, GLOBAL(D1L1), !CLR, , , , );

--P1L53 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[5]~COUT0 at LC_X19_Y7_N5
--operation mode is arithmetic

P1L53_cout_0 = !P1L01 # !P1_safe_q[5];
P1L53 = CARRY(P1L53_cout_0);

--P1L63 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[5]~COUT1 at LC_X19_Y7_N5
--operation mode is arithmetic

P1L63_cout_1 = !P1L01 # !P1_safe_q[5];
P1L63 = CARRY(P1L63_cout_1);


--P1_safe_q[6] is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[6] at LC_X19_Y7_N6
--operation mode is arithmetic

P1_safe_q[6]_carry_eqn = (!P1L01 & P1L53) # (P1L01 & P1L63);
P1_safe_q[6]_lut_out = P1_safe_q[6] $ !P1_safe_q[6]_carry_eqn;
P1_safe_q[6] = DFFEA(P1_safe_q[6]_lut_out, GLOBAL(D1L1), !CLR, , , , );

--P1L83 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[6]~COUT0 at LC_X19_Y7_N6
--operation mode is arithmetic

P1L83_cout_0 = P1_safe_q[6] & !P1L53;
P1L83 = CARRY(P1L83_cout_0);

--P1L93 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[6]~COUT1 at LC_X19_Y7_N6
--operation mode is arithmetic

P1L93_cout_1 = P1_safe_q[6] & !P1L63;
P1L93 = CARRY(P1L93_cout_1);


--P1_safe_q[7] is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[7] at LC_X19_Y7_N7
--operation mode is arithmetic

P1_safe_q[7]_carry_eqn = (!P1L01 & P1L83) # (P1L01 & P1L93);
P1_safe_q[7]_lut_out = P1_safe_q[7] $ P1_safe_q[7]_carry_eqn;
P1_safe_q[7] = DFFEA(P1_safe_q[7]_lut_out, GLOBAL(D1L1), !CLR, , , , );

--P1L14 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[7]~COUT0 at LC_X19_Y7_N7
--operation mode is arithmetic

P1L14_cout_0 = !P1L83 # !P1_safe_q[7];
P1L14 = CARRY(P1L14_cout_0);

--P1L24 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[7]~COUT1 at LC_X19_Y7_N7
--operation mode is arithmetic

P1L24_cout_1 = !P1L93 # !P1_safe_q[7];
P1L24 = CARRY(P1L24_cout_1);


--P1_safe_q[8] is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[8] at LC_X19_Y7_N8
--operation mode is normal

P1_safe_q[8]_carry_eqn = (!P1L01 & P1L14) # (P1L01 & P1L24);
P1_safe_q[8]_lut_out = P1_safe_q[8] $ !P1_safe_q[8]_carry_eqn;
P1_safe_q[8] = DFFEA(P1_safe_q[8]_lut_out, GLOBAL(D1L1), !CLR, , , , );


--J1_ram_rom_data_reg[7] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] at LC_X15_Y7_N4
--operation mode is normal

J1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L7, altera_internal_jtag, J1_ram_rom_data_reg[7], H1_q_b[7], J1L01, VCC, J1L9);


--M1_safe_q[0] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[0] at LC_X12_Y7_N0
--operation mode is arithmetic

M1_safe_q[0] = AMPP_FUNCTION(A1L7, M1_safe_q[0], J1L31, !Q1_Q[0], J1_ram_rom_incr_addr);

--M1L02 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[0]~COUT0 at LC_X12_Y7_N0
--operation mode is arithmetic

M1L02 = AMPP_FUNCTION(M1_safe_q[0]);

--M1L12 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[0]~COUT1 at LC_X12_Y7_N0
--operation mode is arithmetic

M1L12 = AMPP_FUNCTION(M1_safe_q[0]);


--M1_safe_q[1] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[1] at LC_X12_Y7_N1
--operation mode is arithmetic

M1_safe_q[1] = AMPP_FUNCTION(A1L7, M1_safe_q[1], J1L41, !Q1_Q[0], J1_ram_rom_incr_addr, M1L02, M1L12);

--M1L32 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[1]~COUT0 at LC_X12_Y7_N1
--operation mode is arithmetic

M1L32 = AMPP_FUNCTION(M1_safe_q[1], M1L02);

--M1L42 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[1]~COUT1 at LC_X12_Y7_N1
--operation mode is arithmetic

M1L42 = AMPP_FUNCTION(M1_safe_q[1], M1L12);


--M1_safe_q[2] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[2] at LC_X12_Y7_N2
--operation mode is arithmetic

M1_safe_q[2] = AMPP_FUNCTION(A1L7, M1_safe_q[2], J1L51, !Q1_Q[0], J1_ram_rom_incr_addr, M1L32, M1L42);

--M1L62 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[2]~COUT0 at LC_X12_Y7_N2
--operation mode is arithmetic

M1L62 = AMPP_FUNCTION(M1_safe_q[2], M1L32);

--M1L72 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[2]~COUT1 at LC_X12_Y7_N2
--operation mode is arithmetic

M1L72 = AMPP_FUNCTION(M1_safe_q[2], M1L42);


--M1_safe_q[3] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[3] at LC_X12_Y7_N3
--operation mode is arithmetic

M1_safe_q[3] = AMPP_FUNCTION(A1L7, M1_safe_q[3], J1L61, !Q1_Q[0], J1_ram_rom_incr_addr, M1L62, M1L72);

--M1L92 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[3]~COUT0 at LC_X12_Y7_N3
--operation mode is arithmetic

M1L92 = AMPP_FUNCTION(M1_safe_q[3], M1L62);

--M1L03 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[3]~COUT1 at LC_X12_Y7_N3
--operation mode is arithmetic

M1L03 = AMPP_FUNCTION(M1_safe_q[3], M1L72);


--M1_safe_q[4] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[4] at LC_X12_Y7_N4
--operation mode is arithmetic

M1_safe_q[4] = AMPP_FUNCTION(A1L7, M1_safe_q[4], J1L71, !Q1_Q[0], J1_ram_rom_incr_addr, M1L92, M1L03);

--M1L01 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|counter_cella4~COUT at LC_X12_Y7_N4
--operation mode is arithmetic

M1L01 = AMPP_FUNCTION(M1_safe_q[4], M1L92, M1L03);


--M1_safe_q[5] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[5] at LC_X12_Y7_N5
--operation mode is arithmetic

M1_safe_q[5] = AMPP_FUNCTION(A1L7, M1_safe_q[5], J1L81, !Q1_Q[0], J1_ram_rom_incr_addr, M1L01);

--M1L53 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[5]~COUT0 at LC_X12_Y7_N5
--operation mode is arithmetic

M1L53 = AMPP_FUNCTION(M1_safe_q[5]);

--M1L63 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[5]~COUT1 at LC_X12_Y7_N5
--operation mode is arithmetic

M1L63 = AMPP_FUNCTION(M1_safe_q[5]);


--M1_safe_q[6] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[6] at LC_X12_Y7_N6
--operation mode is arithmetic

M1_safe_q[6] = AMPP_FUNCTION(A1L7, M1_safe_q[6], J1L91, !Q1_Q[0], J1_ram_rom_incr_addr, M1L01, M1L53, M1L63);

--M1L83 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[6]~COUT0 at LC_X12_Y7_N6
--operation mode is arithmetic

M1L83 = AMPP_FUNCTION(M1_safe_q[6], M1L53);

--M1L93 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[6]~COUT1 at LC_X12_Y7_N6
--operation mode is arithmetic

M1L93 = AMPP_FUNCTION(M1_safe_q[6], M1L63);


--M1_safe_q[7] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[7] at LC_X12_Y7_N7
--operation mode is arithmetic

M1_safe_q[7] = AMPP_FUNCTION(A1L7, M1_safe_q[7], J1L02, !Q1_Q[0], J1_ram_rom_incr_addr, M1L01, M1L83, M1L93);

--M1L14 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[7]~COUT0 at LC_X12_Y7_N7
--operation mode is arithmetic

M1L14 = AMPP_FUNCTION(M1_safe_q[7], M1L83);

--M1L24 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[7]~COUT1 at LC_X12_Y7_N7
--operation mode is arithmetic

M1L24 = AMPP_FUNCTION(M1_safe_q[7], M1L93);


--M1_safe_q[8] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_0a8:auto_generated|safe_q[8] at LC_X12_Y7_N8
--operation mode is normal

M1_safe_q[8] = AMPP_FUNCTION(A1L7, J1L12, M1_safe_q[8], !Q1_Q[0], J1_ram_rom_incr_addr, M1L01, M1L14, M1L24);


--B1_REGL[6] is ADCINT:inst|REGL[6] at LC_X8_Y9_N2
--operation mode is normal

B1_REGL[6]_sload_eqn = D[6];
B1_REGL[6] = DFFEA(B1_REGL[6]_sload_eqn, GLOBAL(B1L5Q), VCC, , , , );


--J1_ram_rom_data_reg[6] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] at LC_X15_Y7_N2
--operation mode is normal

J1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L7, J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[7], H1_q_b[6], J1L01, VCC, J1L9);


--B1_REGL[5] is ADCINT:inst|REGL[5] at LC_X8_Y11_N2
--operation mode is normal

B1_REGL[5]_sload_eqn = D[5];
B1_REGL[5] = DFFEA(B1_REGL[5]_sload_eqn, GLOBAL(B1L5Q), VCC, , , , );


--J1_ram_rom_data_reg[5] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] at LC_X14_Y7_N2
--operation mode is normal

J1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L7, J1_ram_rom_data_reg[5], J1L01, H1_q_b[5], J1_ram_rom_data_reg[6], VCC, J1L9);


--B1_REGL[4] is ADCINT:inst|REGL[4] at LC_X12_Y11_N2
--operation mode is normal

B1_REGL[4]_sload_eqn = D[4];
B1_REGL[4] = DFFEA(B1_REGL[4]_sload_eqn, GLOBAL(B1L5Q), VCC, , , , );


--J1_ram_rom_data_reg[4] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] at LC_X14_Y7_N5
--operation mode is normal

J1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L7, J1_ram_rom_data_reg[5], J1L01, H1_q_b[4], J1_ram_rom_data_reg[4], VCC, J1L9);