resv.fit.eqn

基于fpga和sopc的用VHDL语言编写的EDA数据采集电路和简易存储示波器

H1_q_b[7]_PORT_A_address_reg = DFFE(H1_q_b[7]_PORT_A_address, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_b[7]_PORT_B_address_reg = DFFE(H1_q_b[7]_PORT_B_address, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_write_enable = WREN;
H1_q_b[7]_PORT_A_write_enable_reg = DFFE(H1_q_b[7]_PORT_A_write_enable, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_write_enable = J1L23;
H1_q_b[7]_PORT_B_write_enable_reg = DFFE(H1_q_b[7]_PORT_B_write_enable, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_clock_0 = GLOBAL(D1L1);
H1_q_b[7]_clock_1 = GLOBAL(A1L7);
H1_q_b[7]_PORT_B_data_out = MEMORY(H1_q_b[7]_PORT_A_data_in_reg, H1_q_b[7]_PORT_B_data_in_reg, H1_q_b[7]_PORT_A_address_reg, H1_q_b[7]_PORT_B_address_reg, H1_q_b[7]_PORT_A_write_enable_reg, H1_q_b[7]_PORT_B_write_enable_reg, , , H1_q_b[7]_clock_0, H1_q_b[7]_clock_1, , , , );
H1_q_b[2] = H1_q_b[7]_PORT_B_data_out[5];

--H1_q_b[3] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_b[3] at M4K_X17_Y7
H1_q_b[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_b[7]_PORT_A_data_in_reg = DFFE(H1_q_b[7]_PORT_A_data_in, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_b[7]_PORT_B_data_in_reg = DFFE(H1_q_b[7]_PORT_B_data_in, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_b[7]_PORT_A_address_reg = DFFE(H1_q_b[7]_PORT_A_address, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_b[7]_PORT_B_address_reg = DFFE(H1_q_b[7]_PORT_B_address, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_write_enable = WREN;
H1_q_b[7]_PORT_A_write_enable_reg = DFFE(H1_q_b[7]_PORT_A_write_enable, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_write_enable = J1L23;
H1_q_b[7]_PORT_B_write_enable_reg = DFFE(H1_q_b[7]_PORT_B_write_enable, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_clock_0 = GLOBAL(D1L1);
H1_q_b[7]_clock_1 = GLOBAL(A1L7);
H1_q_b[7]_PORT_B_data_out = MEMORY(H1_q_b[7]_PORT_A_data_in_reg, H1_q_b[7]_PORT_B_data_in_reg, H1_q_b[7]_PORT_A_address_reg, H1_q_b[7]_PORT_B_address_reg, H1_q_b[7]_PORT_A_write_enable_reg, H1_q_b[7]_PORT_B_write_enable_reg, , , H1_q_b[7]_clock_0, H1_q_b[7]_clock_1, , , , );
H1_q_b[3] = H1_q_b[7]_PORT_B_data_out[4];

--H1_q_b[4] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_b[4] at M4K_X17_Y7
H1_q_b[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_b[7]_PORT_A_data_in_reg = DFFE(H1_q_b[7]_PORT_A_data_in, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_b[7]_PORT_B_data_in_reg = DFFE(H1_q_b[7]_PORT_B_data_in, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_b[7]_PORT_A_address_reg = DFFE(H1_q_b[7]_PORT_A_address, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_b[7]_PORT_B_address_reg = DFFE(H1_q_b[7]_PORT_B_address, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_write_enable = WREN;
H1_q_b[7]_PORT_A_write_enable_reg = DFFE(H1_q_b[7]_PORT_A_write_enable, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_write_enable = J1L23;
H1_q_b[7]_PORT_B_write_enable_reg = DFFE(H1_q_b[7]_PORT_B_write_enable, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_clock_0 = GLOBAL(D1L1);
H1_q_b[7]_clock_1 = GLOBAL(A1L7);
H1_q_b[7]_PORT_B_data_out = MEMORY(H1_q_b[7]_PORT_A_data_in_reg, H1_q_b[7]_PORT_B_data_in_reg, H1_q_b[7]_PORT_A_address_reg, H1_q_b[7]_PORT_B_address_reg, H1_q_b[7]_PORT_A_write_enable_reg, H1_q_b[7]_PORT_B_write_enable_reg, , , H1_q_b[7]_clock_0, H1_q_b[7]_clock_1, , , , );
H1_q_b[4] = H1_q_b[7]_PORT_B_data_out[3];

--H1_q_b[5] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_b[5] at M4K_X17_Y7
H1_q_b[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_b[7]_PORT_A_data_in_reg = DFFE(H1_q_b[7]_PORT_A_data_in, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_b[7]_PORT_B_data_in_reg = DFFE(H1_q_b[7]_PORT_B_data_in, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_b[7]_PORT_A_address_reg = DFFE(H1_q_b[7]_PORT_A_address, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_b[7]_PORT_B_address_reg = DFFE(H1_q_b[7]_PORT_B_address, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_write_enable = WREN;
H1_q_b[7]_PORT_A_write_enable_reg = DFFE(H1_q_b[7]_PORT_A_write_enable, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_write_enable = J1L23;
H1_q_b[7]_PORT_B_write_enable_reg = DFFE(H1_q_b[7]_PORT_B_write_enable, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_clock_0 = GLOBAL(D1L1);
H1_q_b[7]_clock_1 = GLOBAL(A1L7);
H1_q_b[7]_PORT_B_data_out = MEMORY(H1_q_b[7]_PORT_A_data_in_reg, H1_q_b[7]_PORT_B_data_in_reg, H1_q_b[7]_PORT_A_address_reg, H1_q_b[7]_PORT_B_address_reg, H1_q_b[7]_PORT_A_write_enable_reg, H1_q_b[7]_PORT_B_write_enable_reg, , , H1_q_b[7]_clock_0, H1_q_b[7]_clock_1, , , , );
H1_q_b[5] = H1_q_b[7]_PORT_B_data_out[2];

--H1_q_b[6] is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|altsyncram_3fb2:altsyncram1|q_b[6] at M4K_X17_Y7
H1_q_b[7]_PORT_A_data_in = BUS(B1_REGL[7], B1_REGL[6], B1_REGL[5], B1_REGL[4], B1_REGL[3], B1_REGL[2], B1_REGL[1], B1_REGL[0]);
H1_q_b[7]_PORT_A_data_in_reg = DFFE(H1_q_b[7]_PORT_A_data_in, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_data_in = BUS(J1_ram_rom_data_reg[7], J1_ram_rom_data_reg[6], J1_ram_rom_data_reg[5], J1_ram_rom_data_reg[4], J1_ram_rom_data_reg[3], J1_ram_rom_data_reg[2], J1_ram_rom_data_reg[1], J1_ram_rom_data_reg[0]);
H1_q_b[7]_PORT_B_data_in_reg = DFFE(H1_q_b[7]_PORT_B_data_in, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
H1_q_b[7]_PORT_A_address_reg = DFFE(H1_q_b[7]_PORT_A_address, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_address = BUS(M1_safe_q[0], M1_safe_q[1], M1_safe_q[2], M1_safe_q[3], M1_safe_q[4], M1_safe_q[5], M1_safe_q[6], M1_safe_q[7], M1_safe_q[8]);
H1_q_b[7]_PORT_B_address_reg = DFFE(H1_q_b[7]_PORT_B_address, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_PORT_A_write_enable = WREN;
H1_q_b[7]_PORT_A_write_enable_reg = DFFE(H1_q_b[7]_PORT_A_write_enable, H1_q_b[7]_clock_0, , , );
H1_q_b[7]_PORT_B_write_enable = J1L23;
H1_q_b[7]_PORT_B_write_enable_reg = DFFE(H1_q_b[7]_PORT_B_write_enable, H1_q_b[7]_clock_1, , , );
H1_q_b[7]_clock_0 = GLOBAL(D1L1);
H1_q_b[7]_clock_1 = GLOBAL(A1L7);
H1_q_b[7]_PORT_B_data_out = MEMORY(H1_q_b[7]_PORT_A_data_in_reg, H1_q_b[7]_PORT_B_data_in_reg, H1_q_b[7]_PORT_A_address_reg, H1_q_b[7]_PORT_B_address_reg, H1_q_b[7]_PORT_A_write_enable_reg, H1_q_b[7]_PORT_B_write_enable_reg, , , H1_q_b[7]_clock_0, H1_q_b[7]_clock_1, , , , );
H1_q_b[6] = H1_q_b[7]_PORT_B_data_out[1];


--A1L8 is altera_internal_jtag~TDO at JTAG_X1_Y10_N1
A1L8 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !E1L51Q);

--A1L9 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y10_N1
A1L9 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !E1L51Q);

--A1L7 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y10_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !E1L51Q);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y10_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !E1L51Q);


--B1L1Q is ADCINT:inst|current_state~10 at LC_X8_Y10_N6
--operation mode is normal

B1L1Q_lut_out = !B1L5Q;
B1L1Q = DFFEA(B1L1Q_lut_out, GLOBAL(CLK), VCC, , , , );


--B1L3Q is ADCINT:inst|current_state~12 at LC_X8_Y10_N2
--operation mode is normal

B1L3Q_lut_out = B1L2Q # B1L3Q & !EOC;
B1L3Q = DFFEA(B1L3Q_lut_out, GLOBAL(CLK), VCC, , , , );


--Q1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X14_Y9_N5
--operation mode is normal

Q1_Q[2] = AMPP_FUNCTION(A1L7, Q3_Q[0], Q6_Q[2], Q2_Q[2], !E1L2, E1L91);


--J1L23 is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~1 at LC_X14_Y9_N4
--operation mode is normal

J1L23 = AMPP_FUNCTION(Q1_Q[2]);

--J1_ram_rom_incr_write_addr_reg is RAM8B:inst1|altsyncram:altsyncram_component|altsyncram_1p01:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_write_addr_reg at LC_X14_Y9_N4
--operation mode is normal

J1_ram_rom_incr_write_addr_reg = AMPP_FUNCTION(A1L7, J1_ram_rom_load_read_data, VCC, GND);


--D1L1 is CNT10B:inst5|CLK0~7 at LC_X9_Y10_N2
--operation mode is normal

D1L1 = B1L5Q & (WREN # CLK) # !B1L5Q & !WREN & CLK;


--B1_REGL[7] is ADCINT:inst|REGL[7] at LC_X9_Y9_N2
--operation mode is normal

B1_REGL[7]_sload_eqn = D[7];
B1_REGL[7] = DFFEA(B1_REGL[7]_sload_eqn, GLOBAL(B1L5Q), VCC, , , , );


--P1_safe_q[0] is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[0] at LC_X19_Y7_N0
--operation mode is arithmetic

P1_safe_q[0]_lut_out = !P1_safe_q[0];
P1_safe_q[0] = DFFEA(P1_safe_q[0]_lut_out, GLOBAL(D1L1), !CLR, , , , );

--P1L02 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[0]~COUT0 at LC_X19_Y7_N0
--operation mode is arithmetic

P1L02_cout_0 = P1_safe_q[0];
P1L02 = CARRY(P1L02_cout_0);

--P1L12 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[0]~COUT1 at LC_X19_Y7_N0
--operation mode is arithmetic

P1L12_cout_1 = P1_safe_q[0];
P1L12 = CARRY(P1L12_cout_1);


--P1_safe_q[1] is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[1] at LC_X19_Y7_N1
--operation mode is arithmetic

P1_safe_q[1]_lut_out = P1_safe_q[1] $ P1L02;
P1_safe_q[1] = DFFEA(P1_safe_q[1]_lut_out, GLOBAL(D1L1), !CLR, , , , );

--P1L32 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[1]~COUT0 at LC_X19_Y7_N1
--operation mode is arithmetic

P1L32_cout_0 = !P1L02 # !P1_safe_q[1];
P1L32 = CARRY(P1L32_cout_0);

--P1L42 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[1]~COUT1 at LC_X19_Y7_N1
--operation mode is arithmetic

P1L42_cout_1 = !P1L12 # !P1_safe_q[1];
P1L42 = CARRY(P1L42_cout_1);


--P1_safe_q[2] is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[2] at LC_X19_Y7_N2
--operation mode is arithmetic

P1_safe_q[2]_lut_out = P1_safe_q[2] $ !P1L32;
P1_safe_q[2] = DFFEA(P1_safe_q[2]_lut_out, GLOBAL(D1L1), !CLR, , , , );

--P1L62 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[2]~COUT0 at LC_X19_Y7_N2
--operation mode is arithmetic

P1L62_cout_0 = P1_safe_q[2] & !P1L32;
P1L62 = CARRY(P1L62_cout_0);

--P1L72 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[2]~COUT1 at LC_X19_Y7_N2
--operation mode is arithmetic

P1L72_cout_1 = P1_safe_q[2] & !P1L42;
P1L72 = CARRY(P1L72_cout_1);


--P1_safe_q[3] is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[3] at LC_X19_Y7_N3
--operation mode is arithmetic

P1_safe_q[3]_lut_out = P1_safe_q[3] $ P1L62;
P1_safe_q[3] = DFFEA(P1_safe_q[3]_lut_out, GLOBAL(D1L1), !CLR, , , , );

--P1L92 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[3]~COUT0 at LC_X19_Y7_N3
--operation mode is arithmetic

P1L92_cout_0 = !P1L62 # !P1_safe_q[3];
P1L92 = CARRY(P1L92_cout_0);

--P1L03 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[3]~COUT1 at LC_X19_Y7_N3
--operation mode is arithmetic

P1L03_cout_1 = !P1L72 # !P1_safe_q[3];
P1L03 = CARRY(P1L03_cout_1);


--P1_safe_q[4] is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[4] at LC_X19_Y7_N4
--operation mode is arithmetic

P1_safe_q[4]_lut_out = P1_safe_q[4] $ !P1L92;
P1_safe_q[4] = DFFEA(P1_safe_q[4]_lut_out, GLOBAL(D1L1), !CLR, , , , );

--P1L01 is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|counter_cella4~COUT at LC_X19_Y7_N4
--operation mode is arithmetic

P1L01 = P1L23;


--P1_safe_q[5] is CNT10B:inst5|lpm_counter:CQI_rtl_0|cntr_ja7:auto_generated|safe_q[5] at LC_X19_Y7_N5
--operation mode is arithmetic

P1_safe_q[5]_carry_eqn = (!P1L01 & GND) # (P1L01 & VCC);
P1_safe_q[5]_lut_out = P1_safe_q[5] $ P1_safe_q[5]_carry_eqn;