adcint.fit.eqn

基于fpga和sopc的用VHDL语言编写的EDA的ADC0809采样控制电路

--A1L5Q is current_state~11 at LC_X8_Y10_N5
--operation mode is normal

A1L5Q_lut_out = !A1L4Q;
A1L5Q = DFFEA(A1L5Q_lut_out, GLOBAL(CLK), VCC, , , , );


--A1L7Q is current_state~13 at LC_X8_Y10_N4
--operation mode is normal

A1L7Q_lut_out = EOC & A1L6Q;
A1L7Q = DFFEA(A1L7Q_lut_out, GLOBAL(CLK), VCC, , , , );


--A1L12 is OE~0 at LC_X8_Y10_N6
--operation mode is normal

A1L8Q_qfbk = A1L8Q;
A1L12 = A1L7Q # A1L8Q_qfbk;

--A1L8Q is current_state~14 at LC_X8_Y10_N6
--operation mode is normal

A1L8Q_sload_eqn = A1L7Q;
A1L8Q = DFFEA(A1L8Q_sload_eqn, GLOBAL(CLK), VCC, , , , );


--REGL[7] is REGL[7] at LC_X3_Y15_N2
--operation mode is normal

REGL[7]_sload_eqn = D[7];
REGL[7] = DFFEA(REGL[7]_sload_eqn, GLOBAL(A1L8Q), VCC, , , , );


--REGL[6] is REGL[6] at LC_X3_Y14_N2
--operation mode is normal

REGL[6]_sload_eqn = D[6];
REGL[6] = DFFEA(REGL[6]_sload_eqn, GLOBAL(A1L8Q), VCC, , , , );


--REGL[5] is REGL[5] at LC_X6_Y16_N2
--operation mode is normal

REGL[5]_sload_eqn = D[5];
REGL[5] = DFFEA(REGL[5]_sload_eqn, GLOBAL(A1L8Q), VCC, , , , );


--REGL[4] is REGL[4] at LC_X4_Y15_N2
--operation mode is normal

REGL[4]_sload_eqn = D[4];
REGL[4] = DFFEA(REGL[4]_sload_eqn, GLOBAL(A1L8Q), VCC, , , , );


--REGL[3] is REGL[3] at LC_X6_Y15_N2
--operation mode is normal

REGL[3]_sload_eqn = D[3];
REGL[3] = DFFEA(REGL[3]_sload_eqn, GLOBAL(A1L8Q), VCC, , , , );


--REGL[2] is REGL[2] at LC_X7_Y16_N2
--operation mode is normal

REGL[2]_sload_eqn = D[2];
REGL[2] = DFFEA(REGL[2]_sload_eqn, GLOBAL(A1L8Q), VCC, , , , );


--REGL[1] is REGL[1] at LC_X9_Y15_N2
--operation mode is normal

REGL[1]_sload_eqn = D[1];
REGL[1] = DFFEA(REGL[1]_sload_eqn, GLOBAL(A1L8Q), VCC, , , , );


--REGL[0] is REGL[0] at LC_X5_Y15_N2
--operation mode is normal

REGL[0]_sload_eqn = D[0];
REGL[0] = DFFEA(REGL[0]_sload_eqn, GLOBAL(A1L8Q), VCC, , , , );


--A1L4Q is current_state~10 at LC_X8_Y10_N3
--operation mode is normal

A1L4Q_lut_out = !A1L8Q;
A1L4Q = DFFEA(A1L4Q_lut_out, GLOBAL(CLK), VCC, , , , );


--A1L6Q is current_state~12 at LC_X8_Y10_N2
--operation mode is normal

A1L6Q_lut_out = A1L5Q # !EOC & A1L6Q;
A1L6Q = DFFEA(A1L6Q_lut_out, GLOBAL(CLK), VCC, , , , );


--CLK is CLK at PIN_28
--operation mode is input

CLK = INPUT();


--EOC is EOC at PIN_1
--operation mode is input

EOC = INPUT();


--D[7] is D[7] at PIN_20
--operation mode is input

D[7] = INPUT();


--D[6] is D[6] at PIN_19
--operation mode is input

D[6] = INPUT();


--D[5] is D[5] at PIN_18
--operation mode is input

D[5] = INPUT();


--D[4] is D[4] at PIN_17
--operation mode is input

D[4] = INPUT();


--D[3] is D[3] at PIN_16
--operation mode is input

D[3] = INPUT();


--D[2] is D[2] at PIN_15
--operation mode is input

D[2] = INPUT();


--D[1] is D[1] at PIN_14
--operation mode is input

D[1] = INPUT();


--D[0] is D[0] at PIN_13
--operation mode is input

D[0] = INPUT();


--ALE is ALE at PIN_138
--operation mode is output

ALE = OUTPUT(A1L5Q);


--START is START at PIN_139
--operation mode is output

START = OUTPUT(A1L5Q);


--OE is OE at PIN_140
--operation mode is output

OE = OUTPUT(A1L12);


--ADDA is ADDA at PIN_137
--operation mode is output

ADDA = OUTPUT(VCC);


--LOCK0 is LOCK0 at PIN_12
--operation mode is output

LOCK0 = OUTPUT(A1L8Q);


--Q[7] is Q[7] at PIN_168
--operation mode is output

Q[7] = OUTPUT(REGL[7]);


--Q[6] is Q[6] at PIN_167
--operation mode is output

Q[6] = OUTPUT(REGL[6]);


--Q[5] is Q[5] at PIN_166
--operation mode is output

Q[5] = OUTPUT(REGL[5]);


--Q[4] is Q[4] at PIN_165
--operation mode is output

Q[4] = OUTPUT(REGL[4]);


--Q[3] is Q[3] at PIN_164
--operation mode is output

Q[3] = OUTPUT(REGL[3]);


--Q[2] is Q[2] at PIN_163
--operation mode is output

Q[2] = OUTPUT(REGL[2]);


--Q[1] is Q[1] at PIN_162
--operation mode is output

Q[1] = OUTPUT(REGL[1]);


--Q[0] is Q[0] at PIN_161
--operation mode is output

Q[0] = OUTPUT(REGL[0]);