schk.tan.summary

基于fpga和sopc的用VHDL语言编写的EDA序列检测器

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -1.437 ns
From           : DIN
To             : Q[1]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.326 ns
From           : Q[3]
To             : AB[0]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.075 ns
From           : DIN
To             : Q[0]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.776 ns
From           : Q[0]
To             : AB[0]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : Q[2]
To             : Q[0]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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