schk.fit.eqn

基于fpga和sopc的用VHDL语言编写的EDA序列检测器

--Q[2] is Q[2] at LC_X22_Y17_N4
--operation mode is normal

Q[2]_lut_out = !Q[3] & A1L9;
Q[2] = DFFEA(Q[2]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , , , );


--Q[1] is Q[1] at LC_X22_Y17_N9
--operation mode is normal

Q[1]_lut_out = !Q[3] & A1L11;
Q[1] = DFFEA(Q[1]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , , , );


--Q[0] is Q[0] at LC_X22_Y17_N5
--operation mode is normal

Q[0]_lut_out = !Q[3] & !Q[0] & (Q[2] $ DIN);
Q[0] = DFFEA(Q[0]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , , , );


--Q[3] is Q[3] at LC_X22_Y17_N1
--operation mode is normal

Q[3]_lut_out = Q[0] & Q[1] & A1L01;
Q[3] = DFFEA(Q[3]_lut_out, GLOBAL(CLK), !GLOBAL(CLR), , , , );


--A1L71 is reduce_nor~18 at LC_X22_Y17_N6
--operation mode is normal

A1L71 = Q[1] # Q[2] # Q[0] # !Q[3];


--A1L01 is Mux~348 at LC_X22_Y17_N0
--operation mode is normal

A1L01 = DIN & Q[2] & !Q[3];


--A1L11 is Mux~349 at LC_X22_Y17_N8
--operation mode is normal

A1L11 = Q[1] & !Q[0] & (DIN $ Q[2]) # !Q[1] & DIN & Q[0];


--A1L9 is Mux~347 at LC_X22_Y17_N3
--operation mode is normal

A1L9 = Q[1] & !DIN & (Q[2] $ Q[0]) # !Q[1] & Q[2] & (DIN $ !Q[0]);


--DIN is DIN at PIN_3
--operation mode is input

DIN = INPUT();


--CLK is CLK at PIN_2
--operation mode is input

CLK = INPUT();


--CLR is CLR at PIN_4
--operation mode is input

CLR = INPUT();


--AB[3] is AB[3] at PIN_168
--operation mode is output

AB[3] = OUTPUT(VCC);


--AB[2] is AB[2] at PIN_167
--operation mode is output

AB[2] = OUTPUT(GND);


--AB[1] is AB[1] at PIN_166
--operation mode is output

AB[1] = OUTPUT(VCC);


--AB[0] is AB[0] at PIN_165
--operation mode is output

AB[0] = OUTPUT(A1L71);