schk.vhd

基于fpga和sopc的用VHDL语言编写的EDA序列检测器

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SCHK IS
  PORT(DIN, CLK, CLR  : IN STD_LOGIC; --串行输入数据位/工作时钟/复位信号
        AB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --检测结果输出
END SCHK;
ARCHITECTURE behav OF SCHK IS
    SIGNAL Q : INTEGER RANGE 0 TO 8 ;
    SIGNAL D : STD_LOGIC_VECTOR(7 DOWNTO 0);    --8位待检测预置数
BEGIN
    D <= "11100101"  ; --8位待检测预置数：密码：E5H
  PROCESS( CLK, CLR )
  BEGIN
  IF CLR = '1' THEN    Q <= 0 ;
  ELSIF  CLK'EVENT AND CLK='1' THEN  --时钟到来时，判断并处理当前输入的位
 CASE Q IS
  WHEN 0=>  IF DIN = D(7) THEN Q <= 1 ; ELSE Q <= 0 ; END IF ;
  WHEN 1=>  IF DIN = D(6) THEN Q <= 2 ; ELSE Q <= 0 ; END IF ;
  WHEN 2=>  IF DIN = D(5) THEN Q <= 3 ; ELSE Q <= 0 ; END IF ;
  WHEN 3=>  IF DIN = D(4) THEN Q <= 4 ; ELSE Q <= 0 ; END IF ;
  WHEN 4=>  IF DIN = D(3) THEN Q <= 5 ; ELSE Q <= 0 ; END IF ;
  WHEN 5=>  IF DIN = D(2) THEN Q <= 6 ; ELSE Q <= 0 ; END IF ;
  WHEN 6=>  IF DIN = D(1) THEN Q <= 7 ; ELSE Q <= 0 ; END IF ;
  WHEN 7=>  IF DIN = D(0) THEN Q <= 8 ; ELSE Q <= 0 ; END IF ;
  WHEN OTHERS =>  Q <= 0 ;
        END CASE ;
    END IF ;
  END PROCESS ;
  PROCESS( Q )                                 --检测结果判断输出
  BEGIN
      IF Q = 8  THEN  AB <= "1010" ;     --序列数检测正确，输出 "A"
      ELSE              AB <= "1011" ;     --序列数检测错误，输出 "B"
      END IF ;
  END PROCESS ;
END behav ;