freqtest.tan.summary

基于fpga和sopc的用VHDL语言编写的EDA8位16进制频率计

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.702 ns
From           : REG:U2|lpm_ff:lpm_ff_component|dffs[3]
To             : DOUT[3]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.959 ns
From           : CNT:U3|lpm_counter:lpm_counter_component|cntr_6f8:auto_generated|safe_q[31]
To             : CCOUT
From Clock     : FSIN
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'FSIN'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : CNT:U3|lpm_counter:lpm_counter_component|cntr_6f8:auto_generated|safe_q[2]
To             : CNT:U3|lpm_counter:lpm_counter_component|cntr_6f8:auto_generated|safe_q[31]
From Clock     : FSIN
To Clock       : FSIN
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : TESTCTL:U1|Div2CLK
To             : TESTCTL:U1|Div2CLK
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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