singt.map.rpt

基于fpga和sopc的用VHDL语言编写的EDA正弦信号发生器

; Number of WYSIWYG registers                            ; 79    ;
; Number of synthesis-generated registers                ; 270   ;
; Number of cells with combinational logic only          ; 149   ;
; Number of cells with registers only                    ; 157   ;
; Number of cells with combinational logic and registers ; 192   ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 14    ;
; Number of registers using Synchronous Load   ; 29    ;
; Number of registers using Asynchronous Clear ; 255   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 189   ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                          ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; Instance Index ; Instance Name ; Trigger Input Width ; Data Input Width ; Sample Depth ; Trigger Levels ; Advanced Trigger Levels ; Trigger In Used ; Trigger Out Used ; Incremental Trigger Inputs ; Incremental Data Inputs ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; 0              ; sinout        ; 14                  ; 14               ; 1024         ; 1              ; 0                       ; yes             ; no               ; 0                          ; 0                       ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Setting                                                                                                      ;
+----------------+-------------+-------+-------+------------+----------------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode       ; Hierarchy Location                                                               ;
+----------------+-------------+-------+-------+------------+----------------------------------------------------------------------------------+
; 0              ; rom1        ; 8     ; 64    ; Read/Write ; |SINGT|data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated ;
+----------------+-------------+-------+-------+------------+----------------------------------------------------------------------------------+


+-----------+
; Hierarchy ;
+-----------+
SINGT
 |-- lpm_counter:Q1_rtl_0
      |-- cntr_es6:auto_generated
 |-- sld_signaltap:sinout
      |-- sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst
           |-- lpm_counter:\adv_point_3_and_more:advance_pointer_counter
                |-- cntr_bv7:auto_generated
           |-- lpm_shiftreg:info_data_shift_out
           |-- lpm_shiftreg:ram_data_shift_out
           |-- lpm_counter:read_pointer_counter
                |-- cntr_dn7:auto_generated
      |-- altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram
           |-- altsyncram_0j82:auto_generated
      |-- sld_rom_sr:crc_rom_sr
      |-- sld_ela_control:ela_control
           |-- sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm
                |-- sld_mbpmg:\trigger_modules_gen:0:trigger_match
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1