singt.qsf

基于fpga和sopc的用VHDL语言编写的EDA正弦信号发生器

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		SINGT_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:32:12  DECEMBER 02, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1
set_global_assignment -name VHDL_FILE SINGT.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE SINGT.vwf
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name SIGNALTAP_FILE stp2.stp

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_28 -to CLK
set_location_assignment PIN_21 -to DOUT\[0\]
set_location_assignment PIN_41 -to DOUT\[1\]
set_location_assignment PIN_128 -to DOUT\[2\]
set_location_assignment PIN_132 -to DOUT\[3\]
set_location_assignment PIN_133 -to DOUT\[4\]
set_location_assignment PIN_134 -to DOUT\[5\]
set_location_assignment PIN_135 -to DOUT\[6\]
set_location_assignment PIN_136 -to DOUT\[7\]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY SINGT
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE on

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"

# Assembler Assignments
# =====================
set_global_assignment -name STRATIX_JTAG_USER_CODE ED32567
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name GENERATE_HEX_FILE ON

# Simulator Assignments
# =====================
set_global_assignment -name POWER_ESTIMATION_START_TIME "0.0 ns"
set_global_assignment -name GLITCH_DETECTION ON
set_global_assignment -name GLITCH_INTERVAL "1.0 ns"
set_global_assignment -name ESTIMATE_POWER_CONSUMPTION ON
set_global_assignment -name VECTOR_INPUT_SOURCE SINGT.vwf
set_global_assignment -name POWER_ESTIMATION_END_TIME "30 us"

# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP On
set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off

# -----------------------------------------
# start AUTO_INSERT_SLD_NODE_ENTITY(sinout)

	# SignalTap II Assignments
	# ========================
	set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=M4K" -section_id sinout
	set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to CLK -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[0\] -to DOUT\[0\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[1\] -to DOUT\[1\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[2\] -to DOUT\[2\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[3\] -to DOUT\[3\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[4\] -to DOUT\[4\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[5\] -to DOUT\[5\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[6\] -to DOUT\[6\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[7\] -to DOUT\[7\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[8\] -to Q1\[0\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[9\] -to Q1\[1\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[10\] -to Q1\[2\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[11\] -to Q1\[3\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[12\] -to Q1\[4\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[13\] -to Q1\[5\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[0\] -to DOUT\[0\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[1\] -to DOUT\[1\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[2\] -to DOUT\[2\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[3\] -to DOUT\[3\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[4\] -to DOUT\[4\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[5\] -to DOUT\[5\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[6\] -to DOUT\[6\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[7\] -to DOUT\[7\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[8\] -to Q1\[0\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[9\] -to Q1\[1\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[10\] -to Q1\[2\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[11\] -to Q1\[3\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[12\] -to Q1\[4\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[13\] -to Q1\[5\] -section_id sinout
	set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT trigger_in -to Q1\[5\] -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=14" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=14" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=402681344" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=16925" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=9249" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BIT_CNTR_BITS=4" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=1024" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_MEM_ADDRESS_BITS=10" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=1" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id sinout
	set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id sinout

# end AUTO_INSERT_SLD_NODE_ENTITY(sinout)
# ---------------------------------------