gg.mif

基于fpga和sopc的用VHDL语言编写的EDA正弦信号发生器

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.

-- Quartus II generated Memory Initialization File (.mif)

WIDTH=8;
DEPTH=64;

ADDRESS_RADIX=HEX;
DATA_RADIX=BIN;

CONTENT BEGIN
	00  :   11111111;
	01  :   11111110;
	02  :   11111100;
	03  :   11111001;
	04  :   11110101;
	05  :   11101111;
	06  :   11101001;
	07  :   11100001;
	08  :   11011001;
	09  :   11001111;
	0a  :   11000101;
	0b  :   10111010;
	0c  :   10101110;
	0d  :   10100010;
	0e  :   10010110;
	0f  :   10001001;
	10  :   01111100;
	11  :   01110000;
	12  :   01100011;
	13  :   01010111;
	14  :   01001011;
	15  :   01000000;
	16  :   00110101;
	17  :   00101011;
	18  :   00100010;
	19  :   00011010;
	1a  :   00010011;
	1b  :   00001101;
	1c  :   00001000;
	1d  :   00000100;
	1e  :   00000001;
	[1f..20]  :   00000000;
	21  :   00000001;
	22  :   00000100;
	23  :   00001000;
	24  :   00001101;
	25  :   00010011;
	26  :   00011010;
	27  :   00100010;
	28  :   00101011;
	29  :   00110101;
	2a  :   01000000;
	2b  :   01001011;
	2c  :   01010111;
	2d  :   01100011;
	2e  :   01110000;
	2f  :   01111100;
	30  :   10001001;
	31  :   10010110;
	32  :   10100010;
	33  :   10101110;
	34  :   10111010;
	35  :   11000101;
	36  :   11001111;
	37  :   11011001;
	38  :   11100001;
	39  :   11101001;
	3a  :   11101111;
	3b  :   11110101;
	3c  :   11111001;
	3d  :   11111100;
	3e  :   11111110;
	3f  :   11111111;
END;