stp1.stp

基于fpga和sopc的用VHDL语言编写的EDA正弦信号发生器

<session sof_file="">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="sinout" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="sinout" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="3"/>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2005/01/21 08:48:57  #0">
      <clock name="CLK" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="yes" trigger_in_node="Q1[5]" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="DOUT[0]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[1]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[2]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[3]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[4]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[5]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[6]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[7]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="Q1[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[5]" tap_mode="classic" type="register"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire connection_status="true" name="DOUT[0]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[1]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[2]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[3]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[4]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[5]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[6]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[7]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="Q1[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[5]" tap_mode="classic" type="register"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus link="all" name="DOUT" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net name="DOUT[7]"/>
            <net name="DOUT[6]"/>
            <net name="DOUT[5]"/>
            <net name="DOUT[4]"/>
            <net name="DOUT[3]"/>
            <net name="DOUT[2]"/>
            <net name="DOUT[1]"/>
            <net name="DOUT[0]"/>
          </bus>
          <bus link="all" name="Q1" order="msb_to_lsb" radix="hex" state="collapse" type="register">
            <net name="Q1[5]"/>
            <net name="Q1[4]"/>
            <net name="Q1[3]"/>
            <net name="Q1[2]"/>
            <net name="Q1[1]"/>
            <net name="Q1[0]"/>
          </bus>
        </data_view>
        <setup_view>
          <bus link="all" name="DOUT" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net name="DOUT[7]"/>
            <net name="DOUT[6]"/>
            <net name="DOUT[5]"/>
            <net name="DOUT[4]"/>
            <net name="DOUT[3]"/>
            <net name="DOUT[2]"/>
            <net name="DOUT[1]"/>
            <net name="DOUT[0]"/>
          </bus>
          <bus link="all" name="Q1" order="msb_to_lsb" radix="hex" state="collapse" type="register">
            <net name="Q1[5]"/>
            <net name="Q1[4]"/>
            <net name="Q1[3]"/>
            <net name="Q1[2]"/>
            <net name="Q1[1]"/>
            <net name="Q1[0]"/>
          </bus>
        </setup_view>
      </presentation>
      <trigger global_temp="1" is_expanded="true" name="trigger: 2005/01/21 08:48:57  #1" position="center" segment_size="1" trigger_in="rising edge" trigger_out="active high" trigger_type="circular">
        <events>
          <level enabled="yes" type="basic">
            <op_node/>
          </level>
        </events>
      </trigger>
    </signal_set>
    <position_info>
      <single attribute="active tab" value="1"/>
    </position_info>
  </instance>
  <global_info>
    <single attribute="active instance" value="0"/>
    <multi attribute="window position" size="7" value="848,556,374,125,347,50,125"/>
  </global_info>
</session>