dvf.map.rpt

基于fpga和sopc的用VHDL语言编写的EDA数控分频器

; E:/EDA_VHDL_Expt/Chapter5/EP1C3_53_DVF/db/cntr_tr7.tdf                 ; yes             ;
+------------------------------------------------------------------------+-----------------+


+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                  ;
+-----------------------------------+--------------------------+
; Resource                          ; Usage                    ;
+-----------------------------------+--------------------------+
; Logic cells                       ; 465                      ;
; Total combinational functions     ; 325                      ;
; Total 4-input functions           ; 132                      ;
; Total 3-input functions           ; 57                       ;
; Total 2-input functions           ; 32                       ;
; Total 1-input functions           ; 51                       ;
; Total 0-input functions           ; 53                       ;
; Combinational cells for routing   ; 0                        ;
; Total registers                   ; 345                      ;
; Total logic cells in carry chains ; 63                       ;
; Virtual pins                      ; 50                       ;
; I/O pins                          ; 10                       ;
; Total memory bits                 ; 18432                    ;
; Maximum fan-out node              ; altera_internal_jtag~TDO ;
; Maximum fan-out                   ; 220                      ;
; Total fan-out                     ; 1977                     ;
; Average fan-out                   ; 4.04                     ;
+-----------------------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                 ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; Name                                                                                                        ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; sld_signaltap:DVD|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ag82:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 2048         ; 9            ; 2048         ; 9            ; 18432 ; None ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sun May 01 16:17:57 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off DVF -c DVF
Info: Found 2 design units, including 1 entities, in source file DVF.vhd
    Info: Found design unit 1: DVF-one
    Info: Found entity 1: DVF
Info: Found 3 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd
    Info: Found design unit 1: sld_signaltap_pack
    Info: Found design unit 2: sld_signaltap-rtl
    Info: Found entity 1: sld_signaltap
Info: Found 14 design units, including 7 entities, in source file d:/altera/quartus41/libraries/megafunctions/sld_ela_control.vhd
    Info: Found design unit 1: sld_ela_control-rtl
    Info: Found design unit 2: sld_ela_level_seq_mgr-rtl
    Info: Found design unit 3: sld_ela_state_machine-rtl
    Info: Found design unit 4: sld_ela_seg_state_machine-rtl
    Info: Found design unit 5: sld_ela_post_trigger_counter-rtl
    Info: Found design unit 6: sld_ela_segment_mgr-rtl
    Info: Found design unit 7: sld_ela_basic_multi_level_trigger-rtl
    Info: Found entity 1: sld_ela_control
    Info: Found entity 2: sld_ela_level_seq_mgr
    Info: Found entity 3: sld_ela_state_machine
    Info: Found entity 4: sld_ela_seg_state_machine
    Info: Found entity 5: sld_ela_post_trigger_counter
    Info: Found entity 6: sld_ela_segment_mgr
    Info: Found entity 7: sld_ela_basic_multi_level_trigger
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 4 design units, including 2 entities, in source file d:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd
    Info: Found design unit 1: sld_mbpmg-rtl
    Info: Found design unit 2: sld_sbpmg-rtl
    Info: Found entity 1: sld_mbpmg
    Info: Found entity 2: sld_sbpmg
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Warning: LPM_MODULUS input value is 0. It should be within the range of 1 to 2^11. Assume no modulus input
Warning: Assertion warning: LPM_MODULUS input value is 0. It should be within the range of 1 to 2^11. Assume no modulus input
Info: Found 1 design units, including 1 entities, in source file db/cntr_no8.tdf
    Info: Found entity 1: cntr_no8
Warning: LPM_MODULUS input value is 0. It should be within the range of 1 to 2^11. Assume no modulus input
Warning: Assertion warning: LPM_MODULUS input value is 0. It should be within the range of 1 to 2^11. Assume no modulus input
Info: Found 1 design units, including 1 entities, in source file db/cntr_f29.tdf
    Info: Found entity 1: cntr_f29
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_compare.t