dvf.map.rpt

基于fpga和sopc的用VHDL语言编写的EDA数控分频器

           |-- lpm_shiftreg:info_data_shift_out
           |-- lpm_shiftreg:ram_data_shift_out
           |-- lpm_counter:read_pointer_counter
                |-- cntr_ln7:auto_generated
      |-- altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram
           |-- altsyncram_ag82:auto_generated
      |-- sld_rom_sr:crc_rom_sr
      |-- sld_ela_control:ela_control
           |-- sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm
                |-- sld_mbpmg:\trigger_modules_gen:0:trigger_match
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1
                |-- lpm_shiftreg:trigger_condition_deserialize
           |-- sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1
                |-- lpm_counter:post_trigger_counter
                     |-- cntr_no8:auto_generated
           |-- sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr
                |-- lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare
                     |-- altshift:aeb_ext_lat_ffs
                     |-- altshift:agb_ext_lat_ffs
                     |-- comptree:comparator
                          |-- cmpchain:cmp_end
                               |-- comptree:comp
                                    |-- cmpchain:cmp
                                    |-- cmpchain:cmp[0]
                                    |-- cmpchain:cmp[1]
                                    |-- cmpchain:cmp[2]
                                    |-- cmpchain:cmp[3]
                                    |-- cmpchain:cmp[4]
                                    |-- cmpchain:cmp_end
                                    |-- comptree:sub_comptree
                                         |-- cmpchain:cmp
                                         |-- cmpchain:cmp[0]
                                         |-- cmpchain:cmp_end
                                         |-- comptree:sub_comptree
                                              |-- cmpchain:cmp_end
                |-- lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter
                     |-- cntr_f29:auto_generated
           |-- sld_mbpmg:\trigger_in_trigger_module_enabled_gen:trigger_in_match
                |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1
           |-- sld_ela_level_seq_mgr:ela_level_seq_mgr
           |-- sld_ela_state_machine:sm1
           |-- sld_ela_seg_state_machine:sm2
           |-- lpm_shiftreg:trigger_config_deserialize
      |-- sld_acquisition_buffer:sld_acquisition_buffer_inst
           |-- lpm_ff:\gen_non_zero_sample_depth:trigger_address_register
           |-- lpm_counter:\write_address_non_zero_gen:write_pointer_counter
                |-- cntr_vt9:auto_generated
 |-- sld_hub:sld_hub_inst
      |-- sld_dffex:\GEN_IRF:1:IRF
      |-- sld_dffex:\GEN_SHADOW_IRF:1:S_IRF
      |-- sld_dffex:BROADCAST
      |-- sld_rom_sr:HUB_INFO_REG
      |-- lpm_decode:instruction_decoder
           |-- decode_9ie:auto_generated
      |-- sld_dffex:IRF_ENA
      |-- sld_dffex:IRF_ENA_0
      |-- sld_dffex:IRSR
      |-- lpm_shiftreg:jtag_ir_register
      |-- sld_jtag_state_machine:jtag_state_machine
      |-- sld_dffex:RESET


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                                                        ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                                                                                                                                                                                                                                           ;
+---------------------------------------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |DVF                                                                                              ; 415 (6)     ; 295          ; 18432       ; 10   ; 50           ; 120 (4)      ; 140 (2)           ; 155 (0)          ; 63 (0)          ; |DVF                                                                                                                                                                                                                                                                                          ;
;    |lpm_counter:\P_REG:CNT8[0]_rtl_0|                                                             ; 8 (0)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (0)            ; 8 (0)           ; |DVF|lpm_counter:\P_REG:CNT8[0]_rtl_0                                                                                                                                                                                                                                                         ;
;       |cntr_tr7:auto_generated|                                                                   ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; |DVF|lpm_counter:\P_REG:CNT8[0]_rtl_0|cntr_tr7:auto_generated                                                                                                                                                                                                                                 ;
;    |sld_hub:sld_hub_inst|                                                                         ; 112 (35)    ; 71           ; 0           ; 0    ; 0            ; 41 (29)      ; 24 (1)            ; 47 (5)           ; 5 (0)           ; |DVF|sld_hub:sld_hub_inst                                                                                                                                                                                                                                                                     ;
;       |lpm_decode:instruction_decoder|                                                            ; 5 (0)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (0)            ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder                                                                                                                                                                                                                                      ;
;          |decode_9ie:auto_generated|                                                              ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated                                                                                                                                                                                                            ;
;       |lpm_shiftreg:jtag_ir_register|                                                             ; 10 (10)     ; 10           ; 0           ; 0    ; 0            ; 0 (0)        ; 10 (10)           ; 0 (0)            ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register                                                                                                                                                                                                                                       ;
;       |sld_dffex:BROADCAST|                                                                       ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|sld_dffex:BROADCAST                                                                                                                                                                                                                                                 ;
;       |sld_dffex:IRF_ENA_0|                                                                       ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0                                                                                                                                                                                                                                                 ;
;       |sld_dffex:IRF_ENA|                                                                         ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA                                                                                                                                                                                                                                                   ;
;       |sld_dffex:IRSR|                                                                            ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 7 (7)            ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|sld_dffex:IRSR                                                                                                                                                                                                                                                      ;
;       |sld_dffex:RESET|                                                                           ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|sld_dffex:RESET                                                                                                                                                                                                                                                     ;
;       |sld_dffex:\GEN_IRF:1:IRF|                                                                  ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF                                                                                                                                                                                                                                            ;
;       |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|                                                         ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF                                                                                                                                                                                                                                   ;
;       |sld_jtag_state_machine:jtag_state_machine|                                                 ; 21 (21)     ; 19           ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 19 (19)          ; 0 (0)           ; |DVF|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine                                                                                                                                                                                                                           ;