dvf.map.rpt

基于fpga和sopc的用VHDL语言编写的EDA数控分频器

; Ignore SOFT Buffers                                                ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off          ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced     ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70           ; 70            ;
; Auto Carry Chains                                                  ; On           ; On            ;
; Auto Open-Drain Pins                                               ; On           ; On            ;
; Remove Duplicate Logic                                             ; On           ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off          ; Off           ;
; Perform gate-level register retiming                               ; Off          ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On           ; On            ;
; Auto ROM Replacement                                               ; On           ; On            ;
; Auto RAM Replacement                                               ; On           ; On            ;
; Auto Shift Register Replacement                                    ; On           ; On            ;
; Auto Clock Enable Replacement                                      ; On           ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On           ; On            ;
; Auto Resource Sharing                                              ; Off          ; Off           ;
; Allow Any RAM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any ROM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any Shift Register Size For Recognition                      ; Off          ; Off           ;
+--------------------------------------------------------------------+--------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed)                                                                                                                                                                                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; 2:1                ; 8 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |DVF|\P_REG:CNT8[6]                                                                                                                              ;
; 2:1                ; 5 bits    ; 5 LEs         ; 5 LEs                ; 0 LEs                  ; Yes        ; |DVF|sld_signaltap:DVD|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable                                           ;
; 2:1                ; 23 bits   ; 23 LEs        ; 23 LEs               ; 0 LEs                  ; Yes        ; |DVF|sld_signaltap:DVD|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[6] ;
; 2:1                ; 8 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |DVF|sld_signaltap:DVD|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1]  ;
; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |DVF|sld_signaltap:DVD|sld_rom_sr:crc_rom_sr|WORD_SR[3]                                                                                          ;
; 2:1                ; 5 bits    ; 5 LEs         ; 5 LEs                ; 0 LEs                  ; No         ; |DVF|sld_signaltap:DVD|sld_ela_control:ela_control|ela_status[0]                                                                                 ;
; 2:1                ; 5 bits    ; 5 LEs         ; 5 LEs                ; 0 LEs                  ; Yes        ; |DVF|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5]                                                                                          ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |DVF|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[6]                                                                                                    ;
; 18:1               ; 4 bits    ; 48 LEs        ; 32 LEs               ; 16 LEs                 ; Yes        ; |DVF|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1]                                                                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 70    ;
; Number of synthesis-generated cells                    ; 395   ;
; Number of WYSIWYG LUTs                                 ; 70    ;
; Number of synthesis-generated LUTs                     ; 255   ;
; Number of WYSIWYG registers                            ; 63    ;
; Number of synthesis-generated registers                ; 282   ;
; Number of cells with combinational logic only          ; 120   ;
; Number of cells with registers only                    ; 140   ;
; Number of cells with combinational logic and registers ; 205   ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 11    ;
; Number of registers using Synchronous Load   ; 19    ;
; Number of registers using Asynchronous Clear ; 206   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 153   ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                          ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; Instance Index ; Instance Name ; Trigger Input Width ; Data Input Width ; Sample Depth ; Trigger Levels ; Advanced Trigger Levels ; Trigger In Used ; Trigger Out Used ; Incremental Trigger Inputs ; Incremental Data Inputs ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; 0              ; DVD           ; 9                   ; 9                ; 2048         ; 1              ; 0                       ; yes             ; no               ; 9                          ; 9                       ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+


+-----------+
; Hierarchy ;
+-----------+
DVF
 |-- lpm_counter:\P_REG:CNT8[0]_rtl_0
      |-- cntr_tr7:auto_generated
 |-- sld_signaltap:DVD
      |-- sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst
           |-- lpm_counter:\adv_point_3_and_more:advance_pointer_counter
                |-- cntr_vt7:auto_generated