dvf.map.rpt

基于fpga和sopc的用VHDL语言编写的EDA数控分频器

Analysis & Synthesis report for DVF
Sun May 01 16:18:27 2005
Version 4.1 Build 181 06/29/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Multiplexer Restructuring Statistics (No Restructuring Performed)
  5. WYSIWYG Cells
  6. General Register Statistics
  7. SignalTap II Logic Analyzer Settings
  8. Hierarchy
  9. Analysis & Synthesis Resource Utilization by Entity
 10. Analysis & Synthesis Equations
 11. Analysis & Synthesis Source Files Read
 12. Analysis & Synthesis Resource Usage Summary
 13. Analysis & Synthesis RAM Summary
 14. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun May 01 16:18:27 2005    ;
; Quartus II Version          ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name               ; DVF                                      ;
; Top-level Entity Name       ; DVF                                      ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 465                                      ;
; Total pins                  ; 14                                       ;
; Total memory bits           ; 18,432                                   ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C3T144C8  ;               ;
; Disk space/compilation speed tradeoff                              ; Smart        ; Normal        ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; Top-level entity name                                              ; DVF          ; DVF           ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;