stp1.stp

基于fpga和sopc的用VHDL语言编写的EDA数控分频器

<session jtag_chain="ByteBlasterMV [LPT1]" jtag_device="@1: EP1C3 (0x020810DD)" sof_file="DVF.sof">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="DVD" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="DVD" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="3"/>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2005/02/02 13:12:33  #0">
      <clock name="CLK" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="9" reserved_trigger_nodes="9" sample_depth="2048" trigger_in_enable="yes" trigger_in_node="FULL" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="D[0]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[1]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[2]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[3]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[4]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[5]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[6]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[7]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="FOUT" tap_mode="probeonly" type="output pin"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire connection_status="true" name="D[0]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[1]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[2]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[3]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[4]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[5]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[6]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="D[7]" tap_mode="probeonly" type="input pin"/>
          <wire connection_status="true" name="FOUT" tap_mode="probeonly" type="output pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus link="all" name="D" order="msb_to_lsb" radix="hex" state="collapse" type="input pin">
            <net name="D[7]"/>
            <net name="D[6]"/>
            <net name="D[5]"/>
            <net name="D[4]"/>
            <net name="D[3]"/>
            <net name="D[2]"/>
            <net name="D[1]"/>