scan_led.tan.rpt

来自「基于fpga和sopc的用VHDL语言编写的EDA8段数码显示译码器」· RPT 代码 · 共 272 行 · 第 1/2 页

; N/A   ; None         ; 8.041 ns   ; CNT8[2] ; SG[2] ; CLK        ;
; N/A   ; None         ; 8.035 ns   ; CNT8[0] ; SG[6] ; CLK        ;
; N/A   ; None         ; 8.024 ns   ; CNT8[2] ; SG[1] ; CLK        ;
; N/A   ; None         ; 8.011 ns   ; CNT8[2] ; SG[6] ; CLK        ;
; N/A   ; None         ; 7.925 ns   ; CNT8[2] ; BT[0] ; CLK        ;
; N/A   ; None         ; 7.872 ns   ; CNT8[1] ; SG[2] ; CLK        ;
; N/A   ; None         ; 7.852 ns   ; CNT8[1] ; SG[1] ; CLK        ;
; N/A   ; None         ; 7.852 ns   ; CNT8[1] ; SG[6] ; CLK        ;
; N/A   ; None         ; 7.617 ns   ; CNT8[0] ; SG[4] ; CLK        ;
; N/A   ; None         ; 7.607 ns   ; CNT8[0] ; SG[5] ; CLK        ;
; N/A   ; None         ; 7.603 ns   ; CNT8[0] ; SG[3] ; CLK        ;
; N/A   ; None         ; 7.588 ns   ; CNT8[2] ; SG[4] ; CLK        ;
; N/A   ; None         ; 7.581 ns   ; CNT8[2] ; SG[5] ; CLK        ;
; N/A   ; None         ; 7.577 ns   ; CNT8[2] ; SG[3] ; CLK        ;
; N/A   ; None         ; 7.424 ns   ; CNT8[1] ; SG[3] ; CLK        ;
; N/A   ; None         ; 7.419 ns   ; CNT8[1] ; SG[5] ; CLK        ;
; N/A   ; None         ; 7.412 ns   ; CNT8[1] ; SG[4] ; CLK        ;
+-------+--------------+------------+---------+-------+------------+


+----------------------------------------------------------------------------------+
; Minimum tco                                                                      ;
+---------------+------------------+----------------+---------+-------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From    ; To    ; From Clock ;
+---------------+------------------+----------------+---------+-------+------------+
; N/A           ; None             ; 7.412 ns       ; CNT8[1] ; SG[4] ; CLK        ;
; N/A           ; None             ; 7.419 ns       ; CNT8[1] ; SG[5] ; CLK        ;
; N/A           ; None             ; 7.424 ns       ; CNT8[1] ; SG[3] ; CLK        ;
; N/A           ; None             ; 7.577 ns       ; CNT8[2] ; SG[3] ; CLK        ;
; N/A           ; None             ; 7.581 ns       ; CNT8[2] ; SG[5] ; CLK        ;
; N/A           ; None             ; 7.588 ns       ; CNT8[2] ; SG[4] ; CLK        ;
; N/A           ; None             ; 7.603 ns       ; CNT8[0] ; SG[3] ; CLK        ;
; N/A           ; None             ; 7.607 ns       ; CNT8[0] ; SG[5] ; CLK        ;
; N/A           ; None             ; 7.617 ns       ; CNT8[0] ; SG[4] ; CLK        ;
; N/A           ; None             ; 7.852 ns       ; CNT8[1] ; SG[6] ; CLK        ;
; N/A           ; None             ; 7.852 ns       ; CNT8[1] ; SG[1] ; CLK        ;
; N/A           ; None             ; 7.872 ns       ; CNT8[1] ; SG[2] ; CLK        ;
; N/A           ; None             ; 7.925 ns       ; CNT8[2] ; BT[0] ; CLK        ;
; N/A           ; None             ; 8.011 ns       ; CNT8[2] ; SG[6] ; CLK        ;
; N/A           ; None             ; 8.024 ns       ; CNT8[2] ; SG[1] ; CLK        ;
; N/A           ; None             ; 8.035 ns       ; CNT8[0] ; SG[6] ; CLK        ;
; N/A           ; None             ; 8.041 ns       ; CNT8[2] ; SG[2] ; CLK        ;
; N/A           ; None             ; 8.053 ns       ; CNT8[0] ; SG[1] ; CLK        ;
; N/A           ; None             ; 8.069 ns       ; CNT8[0] ; SG[2] ; CLK        ;
; N/A           ; None             ; 8.100 ns       ; CNT8[0] ; BT[0] ; CLK        ;
; N/A           ; None             ; 8.193 ns       ; CNT8[1] ; BT[0] ; CLK        ;
; N/A           ; None             ; 8.312 ns       ; CNT8[2] ; BT[1] ; CLK        ;
; N/A           ; None             ; 8.318 ns       ; CNT8[2] ; BT[2] ; CLK        ;
; N/A           ; None             ; 8.319 ns       ; CNT8[2] ; BT[3] ; CLK        ;
; N/A           ; None             ; 8.324 ns       ; CNT8[2] ; BT[4] ; CLK        ;
; N/A           ; None             ; 8.377 ns       ; CNT8[2] ; SG[0] ; CLK        ;
; N/A           ; None             ; 8.473 ns       ; CNT8[0] ; BT[1] ; CLK        ;
; N/A           ; None             ; 8.488 ns       ; CNT8[0] ; BT[2] ; CLK        ;
; N/A           ; None             ; 8.493 ns       ; CNT8[0] ; BT[3] ; CLK        ;
; N/A           ; None             ; 8.496 ns       ; CNT8[0] ; BT[4] ; CLK        ;
; N/A           ; None             ; 8.541 ns       ; CNT8[1] ; BT[7] ; CLK        ;
; N/A           ; None             ; 8.548 ns       ; CNT8[0] ; SG[0] ; CLK        ;
; N/A           ; None             ; 8.556 ns       ; CNT8[2] ; BT[5] ; CLK        ;
; N/A           ; None             ; 8.566 ns       ; CNT8[2] ; BT[6] ; CLK        ;
; N/A           ; None             ; 8.588 ns       ; CNT8[1] ; BT[1] ; CLK        ;
; N/A           ; None             ; 8.594 ns       ; CNT8[1] ; BT[2] ; CLK        ;
; N/A           ; None             ; 8.595 ns       ; CNT8[1] ; BT[3] ; CLK        ;
; N/A           ; None             ; 8.600 ns       ; CNT8[1] ; BT[4] ; CLK        ;
; N/A           ; None             ; 8.653 ns       ; CNT8[1] ; SG[0] ; CLK        ;
; N/A           ; None             ; 8.710 ns       ; CNT8[2] ; BT[7] ; CLK        ;
; N/A           ; None             ; 8.730 ns       ; CNT8[0] ; BT[5] ; CLK        ;
; N/A           ; None             ; 8.731 ns       ; CNT8[0] ; BT[6] ; CLK        ;
; N/A           ; None             ; 8.738 ns       ; CNT8[0] ; BT[7] ; CLK        ;
; N/A           ; None             ; 8.828 ns       ; CNT8[1] ; BT[5] ; CLK        ;
; N/A           ; None             ; 8.841 ns       ; CNT8[1] ; BT[6] ; CLK        ;
+---------------+------------------+----------------+---------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Aug 02 07:03:24 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off SCAN_LED -c SCAN_LED --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node CLK is an undefined clock
Info: Clock CLK Internal fmax is restricted to 275.03 MHz between source register CNT8[0] and destination register CNT8[2]
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.312 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N2; Fanout = 17; REG Node = 'CNT8[0]'
            Info: 2: + IC(0.645 ns) + CELL(0.292 ns) = 0.937 ns; Loc. = LC_X34_Y16_N9; Fanout = 1; COMB Node = 'add~31'
            Info: 3: + IC(0.508 ns) + CELL(0.867 ns) = 2.312 ns; Loc. = LC_X34_Y16_N0; Fanout = 15; REG Node = 'CNT8[2]'
            Info: Total cell delay = 1.159 ns ( 50.13 % )
            Info: Total interconnect delay = 1.153 ns ( 49.87 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock CLK to destination register is 2.938 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 3; CLK Node = 'CLK'
                Info: 2: + IC(0.758 ns) + CELL(0.711 ns) = 2.938 ns; Loc. = LC_X34_Y16_N0; Fanout = 15; REG Node = 'CNT8[2]'
                Info: Total cell delay = 2.180 ns ( 74.20 % )
                Info: Total interconnect delay = 0.758 ns ( 25.80 % )
            Info: - Longest clock path from clock CLK to source register is 2.938 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 3; CLK Node = 'CLK'
                Info: 2: + IC(0.758 ns) + CELL(0.711 ns) = 2.938 ns; Loc. = LC_X34_Y16_N2; Fanout = 17; REG Node = 'CNT8[0]'
                Info: Total cell delay = 2.180 ns ( 74.20 % )
                Info: Total interconnect delay = 0.758 ns ( 25.80 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock CLK to destination pin BT[6] through register CNT8[1] is 8.841 ns
    Info: + Longest clock path from clock CLK to source register is 2.938 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(0.758 ns) + CELL(0.711 ns) = 2.938 ns; Loc. = LC_X34_Y16_N5; Fanout = 16; REG Node = 'CNT8[1]'
        Info: Total cell delay = 2.180 ns ( 74.20 % )
        Info: Total interconnect delay = 0.758 ns ( 25.80 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.679 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N5; Fanout = 16; REG Node = 'CNT8[1]'
        Info: 2: + IC(1.394 ns) + CELL(0.442 ns) = 1.836 ns; Loc. = LC_X34_Y15_N3; Fanout = 1; COMB Node = 'Mux~54'
        Info: 3: + IC(1.719 ns) + CELL(2.124 ns) = 5.679 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'BT[6]'
        Info: Total cell delay = 2.566 ns ( 45.18 % )
        Info: Total interconnect delay = 3.113 ns ( 54.82 % )
Info: Minimum tco from clock CLK to destination pin SG[4] through register CNT8[1] is 7.412 ns
    Info: + Shortest clock path from clock CLK to source register is 2.938 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(0.758 ns) + CELL(0.711 ns) = 2.938 ns; Loc. = LC_X34_Y16_N5; Fanout = 16; REG Node = 'CNT8[1]'
        Info: Total cell delay = 2.180 ns ( 74.20 % )
        Info: Total interconnect delay = 0.758 ns ( 25.80 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Shortest register to pin delay is 4.250 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N5; Fanout = 16; REG Node = 'CNT8[1]'
        Info: 2: + IC(0.596 ns) + CELL(0.442 ns) = 1.038 ns; Loc. = LC_X34_Y16_N6; Fanout = 1; COMB Node = 'Mux~93'
        Info: 3: + IC(1.088 ns) + CELL(2.124 ns) = 4.250 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'SG[4]'
        Info: Total cell delay = 2.566 ns ( 60.38 % )
        Info: Total interconnect delay = 1.684 ns ( 39.62 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Aug 02 07:03:24 2005
    Info: Elapsed time: 00:00:00