scan_led.vhd

基于fpga和sopc的用VHDL语言编写的EDA8段数码显示译码器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SCAN_LED IS                                    
    PORT (   CLK   : IN STD_LOGIC; 
              SG   : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);  --段控制信号输出
              BT   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );--位控制信号输出
 END;
ARCHITECTURE one OF SCAN_LED IS
    SIGNAL CNT8  : STD_LOGIC_VECTOR(2 DOWNTO 0); 
    SIGNAL    A  : INTEGER RANGE 0 TO 15;
BEGIN
P1: PROCESS( CNT8 )
    BEGIN
        CASE  CNT8 IS
          WHEN "000" =>  BT <= "00000001" ; A <= 1 ;
          WHEN "001" =>  BT <= "00000010" ; A <= 3 ; 
          WHEN "010" =>  BT <= "00000100" ; A <= 5 ;
          WHEN "011" =>  BT <= "00001000" ; A <= 7 ;
          WHEN "100" =>  BT <= "00010000" ; A <= 9 ;
          WHEN "101" =>  BT <= "00100000" ; A <= 11 ;
          WHEN "110" =>  BT <= "01000000" ; A <= 13 ;
          WHEN "111" =>  BT <= "10000000" ; A <= 15 ;
          WHEN OTHERS =>  NULL ;
        END CASE ;
     END PROCESS P1;
    P2: PROCESS(CLK)
        BEGIN
         IF CLK'EVENT AND CLK = '1' THEN CNT8 <= CNT8 + 1;   
         END IF;
	   END PROCESS P2 ;   
     P3: PROCESS( A ) --译码电路
      BEGIN
       CASE  A  IS
        WHEN 0  => SG <= "0111111";  WHEN 1  => SG <= "0000110"; 
        WHEN 2  => SG <= "1011011";  WHEN 3  => SG <= "1001111"; 
        WHEN 4  => SG <= "1100110";  WHEN 5  => SG <= "1101101"; 
        WHEN 6  => SG <= "1111101";  WHEN 7  => SG <= "0000111";
        WHEN 8  => SG <= "1111111";  WHEN 9  => SG <= "1101111"; 
        WHEN 10 => SG <= "1110111";  WHEN 11 => SG <= "1111100";
        WHEN 12 => SG <= "0111001";  WHEN 13 => SG <= "1011110"; 
        WHEN 14 => SG <= "1111001";  WHEN 15 => SG <= "1110001";
        WHEN OTHERS =>  NULL ;
       END CASE ;
      END PROCESS P3;    
END;