scan_led.fit.rpt

基于fpga和sopc的用VHDL语言编写的EDA8段数码显示译码器

; C4s                        ; 18 / 16,320 ( < 1 % ) ;
; Direct links               ; 5 / 21,944 ( < 1 % )  ;
; Global clocks              ; 1 / 8 ( 12 % )        ;
; LAB clocks                 ; 1 / 240 ( < 1 % )     ;
; LUT chains                 ; 0 / 5,382 ( 0 % )     ;
; Local interconnects        ; 19 / 21,944 ( < 1 % ) ;
; M4K buffers                ; 0 / 720 ( 0 % )       ;
; R4s                        ; 0 / 14,640 ( 0 % )    ;
+----------------------------+-----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 9.00) ; Number of LABs  (Total = 2) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 0                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 0                           ;
; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 1                           ;
; 9                                          ; 0                           ;
; 10                                         ; 1                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 0.50) ; Number of LABs  (Total = 2) ;
+------------------------------------+-----------------------------+
; 1 Clock                            ; 1                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 9.00) ; Number of LABs  (Total = 2) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 1                           ;
; 9                                           ; 0                           ;
; 10                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 8.50) ; Number of LABs  (Total = 2) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 0                           ;
; 2                                               ; 0                           ;
; 3                                               ; 0                           ;
; 4                                               ; 0                           ;
; 5                                               ; 0                           ;
; 6                                               ; 0                           ;
; 7                                               ; 0                           ;
; 8                                               ; 1                           ;
; 9                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 2.00) ; Number of LABs  (Total = 2) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 0                           ;
; 3                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Aug 02 07:03:14 2005
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off SCAN_LED -c SCAN_LED
Info: Selected device EP1C6Q240C8 for design SCAN_LED
Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EP1C12Q240C8 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal CLK to use Global clock in PIN 28
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start DSP scan-chain inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 1.869 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X34_Y16; Fanout = 17; REG Node = 'CNT8[0]'
    Info: 2: + IC(0.063 ns) + CELL(0.590 ns) = 0.653 ns; Loc. = LAB_X34_Y16; Fanout = 1; COMB Node = 'add~31'
    Info: 3: + IC(0.349 ns) + CELL(0.867 ns) = 1.869 ns; Loc. = LAB_X34_Y16; Fanout = 15; REG Node = 'CNT8[2]'
    Info: Total cell delay = 1.457 ns ( 77.96 % )
    Info: Total interconnect delay = 0.412 ns ( 22.04 % )
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Aug 02 07:03:20 2005
    Info: Elapsed time: 00:00:06