mux21a.fit.eqn

基于fpga和sopc的用VHDL语言编写的EDA组合电路的设计

--A1L5 is y~8 at LC_X20_Y13_N2
--operation mode is normal

A1L5 = a & (b # !s) # !a & s & b;


--b is b at PIN_152
--operation mode is input

b = INPUT();


--a is a at PIN_28
--operation mode is input

a = INPUT();


--s is s at PIN_233
--operation mode is input

s = INPUT();


--y is y at PIN_174
--operation mode is output

y = OUTPUT(A1L5);