mux21a.vhd

基于fpga和sopc的用VHDL语言编写的EDA组合电路的设计

ENTITY mux21a IS
  PORT ( a, b, s: IN  BIT; 
              y : OUT BIT  );
END ENTITY mux21a;
ARCHITECTURE one OF mux21a IS
 BEGIN
   PROCESS (a,b,s) 
BEGIN
     IF s = '0'  THEN
        y <= a ; ELSE 
y <= b ;
END IF;
   END PROCESS;
END ARCHITECTURE one ;