mux21a.fit.summary

基于fpga和sopc的用VHDL语言编写的EDA组合电路的设计

Flow Status : Successful - Tue Aug 02 06:47:49 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : mux21a
Top-level Entity Name : mux21a
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Production
Total logic elements : 1 / 5,980 ( < 1 % )
Total pins : 4 / 185 ( 2 % )
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )