hours_out.vhd

来自「Bcode_s_m_h.rar实现GPSB码接收、译码等工程」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity hours_out is
  port(quit_in:in std_logic_vector(25 downto 0);
       qa:out std_logic_vector(1 downto 0);
       qb:out std_logic_vector(3 downto 0);
       clk,j_in:in std_logic);
end hours_out;
architecture a of hours_out is
begin 
process(clk,j_in)
begin
if(clk'event and clk='1')then
  if(j_in='1')then 
    qa<=quit_in(23 downto 22);
    qb<=quit_in(20 downto 17);
  else
    null;
  end if;
end if;
end process;
end a;