📄 counter_time.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\bcode_s_m_h\counter_time.rpt
counter_time
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\bcode_s_m_h\counter_time.rpt
counter_time
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 clk
Device-Specific Information: e:\bcode_s_m_h\counter_time.rpt
counter_time
** EQUATIONS **
b_data : INPUT;
clk : INPUT;
-- Node name is ':13' = 'n0'
-- Equation name is 'n0', location is LC5_B10, type is buried.
n0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = b_data & !n0;
-- Node name is ':12' = 'n1'
-- Equation name is 'n1', location is LC4_B10, type is buried.
n1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = b_data & !n0 & n1
# b_data & n0 & !n1;
-- Node name is ':11' = 'n2'
-- Equation name is 'n2', location is LC6_B10, type is buried.
n2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = b_data & !n1 & n2
# b_data & !n0 & n2
# b_data & n0 & n1 & !n2;
-- Node name is ':10' = 'n3'
-- Equation name is 'n3', location is LC8_B10, type is buried.
n3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = b_data & !_LC7_B10 & n3
# b_data & _LC7_B10 & !n3;
-- Node name is ':9' = 'n4'
-- Equation name is 'n4', location is LC4_B6, type is buried.
n4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = b_data & !_LC1_B10 & n4
# b_data & _LC1_B10 & !n4;
-- Node name is ':8' = 'n5'
-- Equation name is 'n5', location is LC5_B6, type is buried.
n5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = b_data & !n4 & n5
# b_data & !_LC1_B10 & n5
# b_data & _LC1_B10 & n4 & !n5;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC1_B6;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC3_B6;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC8_B6;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC2_B6;
-- Node name is '|LPM_ADD_SUB:85|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B10', type is buried
_LC7_B10 = LCELL( _EQ007);
_EQ007 = n0 & n1 & n2;
-- Node name is '|LPM_ADD_SUB:85|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ008);
_EQ008 = n0 & n1 & n2 & n3;
-- Node name is '~279~1'
-- Equation name is '~279~1', location is LC3_B10, type is buried.
-- synthesized logic cell
_LC3_B10 = LCELL( _EQ009);
_EQ009 = !b_data & !n2 & n3;
-- Node name is '~279~2'
-- Equation name is '~279~2', location is LC2_B10, type is buried.
-- synthesized logic cell
_LC2_B10 = LCELL( _EQ010);
_EQ010 = _LC3_B10 & !n0 & !n4;
-- Node name is ':279'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = LCELL( _EQ011);
_EQ011 = _LC2_B10 & !n1 & n5;
-- Node name is '~295~1'
-- Equation name is '~295~1', location is LC6_B6, type is buried.
-- synthesized logic cell
_LC6_B6 = LCELL( _EQ012);
_EQ012 = n0 & n4 & !n5;
-- Node name is ':377'
-- Equation name is '_LC8_B6', type is buried
_LC8_B6 = LCELL( _EQ013);
_EQ013 = _LC2_B6
# _LC3_B10 & _LC6_B6 & !n1;
-- Node name is ':389'
-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = LCELL( _EQ014);
_EQ014 = _LC2_B10 & n1 & !n5
# _LC8_B6;
-- Node name is ':401'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = LCELL( _EQ015);
_EQ015 = _LC8_B6
# _LC2_B10 & n1 & !n5;
Project Information e:\bcode_s_m_h\counter_time.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 28,448K
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