counter_time.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter_time is
port(clk,b_data:in std_logic;
     q:out std_logic_vector(3 downto 0));
end counter_time;
architecture a of counter_time is
  signal k:std_logic:='1';
  signal n:integer range 0 to 40;
  signal q_out: std_logic_vector(3 downto 0);
begin
  process(b_data)
  begin
  if((b_data and b_data)='1')then
  k<='1';
  else
  k<='0';
  end if;
  end process;
process(clk,k)
begin
  if(clk'event and clk='1')then
  if(k='1')then 
  n<=n+1;
  else
   n<=0;
  end if;
  end if;
end process;
process(n)
begin
  if(n=40 and b_data='0')then
  q_out<="1111";
  elsif(n=25 and b_data='0')then
  q_out<="0111";
  elsif(n=10 and b_data='0')then
  q_out<="0011";
  else
  q_out<="0000";
  end if;
end process;
q<=q_out;
end a;